ISL23315TFUZ-T7A Intersil, ISL23315TFUZ-T7A Datasheet

IC DGTL POT 256POS 100K 10MSOP

ISL23315TFUZ-T7A

Manufacturer Part Number
ISL23315TFUZ-T7A
Description
IC DGTL POT 256POS 100K 10MSOP
Manufacturer
Intersil
Series
XDCP™r
Datasheet

Specifications of ISL23315TFUZ-T7A

Taps
256
Resistance (ohms)
100K
Number Of Circuits
1
Temperature Coefficient
75 ppm/°C Typical
Memory Type
Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
10-MSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL23315TFUZ-T7A
Manufacturer:
Intersil
Quantity:
250
Single, Low Voltage Digitally Controlled Potentiometer
(XDCP™)
ISL23315
The ISL23315 is a volatile, low voltage, low noise, low power, I
Bus
which integrates DCP core, wiper switches and control logic on
a monolithic CMOS integrated circuit.
The digitally controlled potentiometer is implemented with a
combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I
volatile Wiper Register (WR) that can be directly written to and
read by the user. The contents of the WR controls the position
of the wiper. When powered on, the ISL23315’s wiper will
always commence at mid-scale (128 tap position).
The low voltage, low power consumption, and small package
of the ISL23315 make it an ideal choice for use in battery
operated equipment. In addition, the ISL23315 has a V
pin allowing down to 1.2V bus operation, independent from the
V
directly to the ISL23315 without passing through a voltage
level shifter.
The DCP can be used as a three-terminal potentiometer or as a
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal processing.
Applications
• Power supply margining
• RF power amplifier bias compensation
• LCD bias compensation
• Laser diode bias compensation
2
December 15, 2010
FN7778.0
CC
C bus interface. The potentiometer has an associated
FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP
10000
value. This allows for low logic levels to be connected
8000
6000
4000
2000
, 256 Taps, single digitally controlled potentiometer (DCP),
0
0
POSITION, 10k DCP
50
TAP POSITION (DECIMAL)
100
1
150
200
LOGIC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
2
250
C
1-888-INTERSIL or 1-888-468-3774
Features
• 256 resistor taps
• I
• Wiper resistance: 70Ω typical @ V
• Shutdown Mode - forces the DCP into an end-to-end open
• Power-on preset to mid-scale (128 tap position)
• Standby current <2.5µA max
• Shutdown current <2µA max
• Power supply
• DCP terminal voltage from 0V to V
• 10kΩ, 50kΩ or 100kΩ total resistance
• Extended industrial temperature range: -40
• 10 Ld MSOP or 10 Ld µTQFN packages
• Pb-free (RoHS compliant)
- No additional level translator for low bus supply
- Two address pins allow up to four devices per bus
circuit and R
- V
- V
ISL23315
2
C serial interface
All other trademarks mentioned are the property of their respective owners
CC
LOGIC
= 1.7V to 5.5V analog power supply
= 1.2V to 5.5V I
V
REF
W
FIGURE 2. V
is shorted to R
|
Copyright Intersil Americas Inc. 2010. All Rights Reserved
2
REF
C bus/logic power supply
+
-
ISL28114
ADJUSTMENT
L
internally
CC
CC
= 3.3V
°
C to +125
V
REF_M
°
C

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ISL23315TFUZ-T7A Summary of contents

Page 1

... FIGURE 2. V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners = 3.3V CC internally ...

Page 2

Block Diagram V LOGIC SCL SDA I/O A1 BLOCK A0 Pin Configurations ISL23315 (10 LD MSOP) TOP VIEW V 1 LOGIC SCL 2 SDA ISL23315 (10 LD µTQFN) TOP VIEW SCL 1 SDA 2 A0 ...

Page 3

... Ordering Information PART NUMBER (Note 5) PART MARKING ISL23315TFUZ (Notes 1, 3) 3315T ISL23315UFUZ (Notes 1, 3) 3315U ISL23315WFUZ (Notes 1, 3) 3315W ISL23315TFRUZ-T7A (Notes ISL23315TFRUZ-TK (Notes ISL23315UFRUZ-T7A (Notes ISL23315UFRUZ-TK (Notes ISL23315WFRUZ-T7A (Notes ISL23315WFRUZ-TK (Notes NOTES: 1. Add “-T*” suffix for Tape and Reel option. Please refer to 2 ...

Page 4

... Thermal Resistance (Typical MSOP Package (Notes µTQFN Package (Notes Maximum Junction Temperature (Plastic Package .+150°C Storage Temperature Range .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C V Supply Voltage 1. Supply Voltage ...

Page 5

Analog Specifications V CC stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER VOLTAGE DIVIDER MODE ( RH; measured at RW, unloaded) CC INL Integral non-linearity, guaranteed (Note 13) monotonic ...

Page 6

Analog Specifications V CC stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER R Offset, wiper at 0 position offset (Note 16) TCR Resistance temperature coefficient (Note 19) Operating Specifications V stated. Boldface limits ...

Page 7

Operating Specifications V stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER tShdnRec DCP recall time from shutdown mode ramp rate CC, LOGIC CC , LOGIC Ramp (Note 21) Serial ...

Page 8

Serial Interface Specification SYMBOL PARAMETER t STOP Condition Set-up Time SU:STO t STOP Condition Hold Time for Read HD:STO or Write t Output Data Hold Time DH t SDA and SCL Rise Time R t SDA and SCL Fall Time ...

Page 9

Timing Diagrams SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) A0 and A1 Pin Timing START SCL SDA A0, A1 Typical Performance Curves 0.4 0.2 0 -0.2 -0 100 TAP POSITION ...

Page 10

Typical Performance Curves 0.4 0.2 0 -0.2 -0 100 TAP POSITION (DECIMAL) FIGURE 5. 10k INL vs TAP POSITION, V 0.4 0.2 0 -0.2 -0 100 TAP POSITION (DECIMAL) FIGURE 7. 10k RDNL vs TAP POSITION, ...

Page 11

Typical Performance Curves 100 TAP POSITION (DECIMAL) FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, V 300 250 200 150 100 115 TAP POSITION (DECIMAL) FIGURE ...

Page 12

Typical Performance Curves 115 TAP POSITION (DECIMAL) FIGURE 17. 100k TCv vs TAP POSITION 10mV/DIV 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH 1V/DIV 1µs/DIV SCL 9TH CLOCK OF THE DATA BYTE ...

Page 13

Typical Performance Curves CH1: 0.5V/DIV, 0.2µs/DIV RH PIN CH2: 0.2V/DIV, 0.2µs/DIV RW PIN R = 10k TOTAL -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP FIGURE 23. 10k -3dB CUT OFF FREQUENCY Functional Pin Descriptions Potentiometers Pins RH AND RL The ...

Page 14

RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL23315 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between R ...

Page 15

SCL SDA START FIGURE 26. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START FIGURE 27. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS ...

Page 16

Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23315 responds with an ACK. The data ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...

Page 18

Mini Small Outline Plastic Packages (MSOP -B- INDEX 1 2 0.20 (0.008) AREA TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE - 0.10 (0.004) b -H- - 0.20 (0.008) SIDE VIEW 0.20 ...

Page 19

Package Outline Drawing L10.2.1x1.6A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 2.10 B 0.10 2X TOP VIEW (10 X 0.20) (10X 0.60) (2.00) (0.80) (1.30) (6X 0.50 ) (2.50) TYPICAL RECOMMENDED LAND PATTERN 19 ISL23315 ...

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