XC3S400AN-4FG400I Xilinx Inc, XC3S400AN-4FG400I Datasheet - Page 110

• Manufacturer Part Number: XC3S400AN-4FG400I
• Description: IC FPGA SPARTAN 3AN 400FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S400AN-4FG400I

• Number Of Logic Elements/cells: 8064
• Number Of Labs/clbs: 896
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FGG676: 676-Ball Fine-Pitch Ball Grid Array
The 676-ball fine-pitch ball grid array, FGG676, supports the XC3S1400AN FPGA.
Table 82
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as
defined in
The XC3S1400AN has 17 unconnected balls, indicated as N.C. in
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 82: Spartan-3AN FGG676 Pinout
DS557 (v4.1) April 1, 2011
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lists all the FGG676 package pins. They are sorted by bank number and then by pin name. Pins that form a
Table
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L05N_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0/VREF_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
62).
Pin Name
FGG676
Ball
G20
G19
C22
D22
C23
D23
G17
H17
C21
D21
C20
D20
H15
G15
C18
D18
F20
F19
A22
B23
B21
E21
K16
E17
F17
A20
B20
A19
B19
J16
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 82: Spartan-3AN FGG676 Pinout (Cont’d)
Bank
Table 82
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Spartan-3AN FPGA Family: Pinout Descriptions
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0/VREF_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/GCLK5
IO_L25P_0/GCLK4
IO_L26N_0/GCLK7
IO_L26P_0/GCLK6
IO_L27N_0/GCLK9
IO_L27P_0/GCLK8
IO_L28N_0/GCLK11
IO_L28P_0/GCLK10
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0
IO_L32N_0/VREF_0
IO_L32P_0
and
Figure
Pin Name
24.
FGG676
Ball
C17
D17
D16
G13
C13
D13
D11
C11
A18
B18
B17
E15
F15
C16
C15
A15
B15
F14
E14
K14
A14
B14
F13
B13
B12
A12
C12
F12
E12
J14
VREF
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
110