XC3S400-4PQ208C Xilinx Inc, XC3S400-4PQ208C Datasheet

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R DS099 December 4, 2009 This document includes all four modules of the Spartan Module 1: Spartan-3 FPGA Family: Introduction and Ordering Information DS099-1 (v2.5) December 4, 2009 • Introduction • Features • Architectural Overview • Array Sizes and Resources ...

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R DS099 December 4, 2009 Product Specification ...

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... XC3S1000 1M 17,280 XC3S1500 1.5M 29,952 XC3S2000 2M 46,080 XC3S4000 4M 62,208 XC3S5000 5M 74,880 104 Notes: 1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" Logic Cells/CLB x 1.125 effectiveness. 2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family. ...

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... Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. Notes: 1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices are shown with dashed lines. The XC3S50 has only the block RAM column on the far left • ...

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R Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configura- tion latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a ...

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... XC3S1000 - - - - XC3S1500 - - - - XC3S2000 - - - - XC3S4000 - - - - XC3S5000 - - - - Notes: 1. The CP132, CPG132, FG1156, and FGG1156 packages are being discontinued and are not recommended for new designs. See http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm 2. All device options listed in a given package column are pin-compatible. 3. User = Single-ended user I/O pins. Diff = Differential I/O pairs. ...

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... Device Type Speed Grade Temperature Range Figure 2: Spartan-3 QFP Package Marking Example for Part Number XC3S400-4PQ208C Temperature Range Figure 3: Spartan-3 BGA Package Marking Example for Part Number XC3S1000-4FT256C Figure 4: Spartan-3 CP132 and CPG132 Package Marking Example for XC3S50-4CP132C DS099-1 (v2.5) December 4, 2009 ...

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... Standard Performance (1) XC3S200 -5 High Performance XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range. 2. The CP132, CPG132, FG1156, and FGG1156 packages are being discontinued and are not recommended for new designs. See http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm 8 ...

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... Added information on Pb-free packaging options. 01/17/05 1.4 Referenced Spartan-3 XA Automotive FPGA families in XC3S2000FG456, XC3S4000FG676 options to revision code, fabrication facility code, and process technology code. 08/19/05 1.5 Added package markings for BGA packages differential (complementary single-ended) HSTL and SSTL I/O standards. ...

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Spartan-3 FPGA Family: Introduction and Ordering Information 10 10 www.xilinx.com R DS099-1 (v2.5) December 4, 2009 Product Specification ...

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R DS099-2 (v2.5) December 4, 2009 Design Documentation Available ® The functionality of the Spartan -3 FPGA family is described in the following documents. The topics covered in each guide are listed below. • UG331: Spartan-3 Generation FPGA User Guide ...

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Spartan-3 FPGA Family: Functional Description IOBs For additional information, refer to the “Using I/O Resources” chapter in UG331. IOB Overview The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal logic. A simplified ...

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TCE OTCLK1 CK SR OCE OTCLK2 IQ1 D CE ICLK1 CK SR ICE IQ2 D CE ICLK2 CK SR ...

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Spartan-3 FPGA Family: Functional Description According to Figure 5, the clock line OTCLK1 connects the CK inputs of the upper registers on the output and three-state paths. Similarly, OTCLK2 connects the CK inputs for the lower registers on the output ...

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R DCM 180˚ 0˚ CLK1 DDR MUX D2 Q2 CLK2 Figure 6: Clocking the DDR Register Pull-Up and Pull-Down Resistors The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os. ...

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Spartan-3 FPGA Family: Functional Description control IOSTANDARD, refer to the “Using I/O Resources” chapter in UG331. Together with placing the appropriate I/O symbol, two exter- nally applied voltage levels, V CCO desired signal standard. The V CCO the output driver. ...

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R DCI answers these concerns by providing two kinds of on-chip terminations: Parallel terminations make use of an integrated resistor network. Series terminations result from controlling the impedance of output drivers. DCI actively adjusts both parallel and series terminations to ...

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Spartan-3 FPGA Family: Functional Description Table 9: DCI I/O Standards (Continued) Category of Signal Signal Standard Standard (IOSTANDARD) Stub Series SSTL18_I_DCI Terminated Logic SSTL2_I_DCI SSTL2_II_DCI DIFF_SSTL2_II_DCI Differential Low-Voltage LVDS_25_DCI Differential LVDSEXT_25_DCI Signaling Notes: 1. DCI signal standards are not supported ...

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R Table 10: DCI Terminations Termination Controlled impedance output driver Controlled output driver with half impedance Single resistor Split resistors Split resistors with output driver impedance fixed to 25Ω Notes: 1. The value equivalent to the characteristic ...

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Spartan-3 FPGA Family: Functional Description The DCI feature operates independently for each of the device’s eight banks. Each bank has an ‘N’ reference pin (VRN) and a ‘P’ reference pin, (VRP), to calibrate driver and termination resistance. Only when using ...

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R 2. Set all V lines associated with the (interconnected) CCO bank to the same voltage level. 3. The V levels used by all standards assigned to the CCO I/Os of the (interconnected) bank(s) must agree. The Xilinx development software ...

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Spartan-3 FPGA Family: Functional Description . Switch Matrix SHIFTOUT SHIFTIN CLB Overview For more details on the CLBs, refer to the “Using Config- urable Logic Blocks” chapter in UG331. The Configurable Logic Blocks (CLBs) constitute the main logic resource for ...

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R Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can depending on the slice. In this position, the ...

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Spartan-3 FPGA Family: Functional Description The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. The carry chain enters the slice as CIN and exits as COUT. Five multiplexers control the chain: ...

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... Arrangement of RAM Blocks on Die The XC3S50 has one column of block RAM. The Spartan-3 devices ranging from the XC3S200 to XC3S2000 have two columns of block RAM. The XC3S4000 and XC3S5000 have four columns. The position of the columns on the die is shown in Figure 1, page 4 ...

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Spartan-3 FPGA Family: Functional Description RAMB16_Sw WEA ENA SSRA CLKA ADDRA[r –1:0] A DIA[w –1:0] A DIPA[3:0] WEB ENB SSRB CLKB ADDRB[r –1:0] B DIB[w –1:0] B DIPB[3:0] (a) Dual-Port Notes and w are integers representing the total ...

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R Table 12: Block RAM Port Signals (Continued) Port A Port B Signal Signal Signal Description Name Data Output DOA Bus Parity Data DOPA Output(s) Write Enable WEA Clock Enable ENA Set/Reset SSRA Clock CLKA DS099-2 (v2.5) December 4, 2009 ...

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Spartan-3 FPGA Family: Functional Description Port Aspect Ratios On a given port possible to select a number of different possible widths (w – p) for the DI/DO buses as shown in Table 13. These two buses always have ...

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R CLK WE DI ADDR DO 0000 EN DISABLED Figure 13: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that location is ...

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Spartan-3 FPGA Family: Functional Description CLK WE DI ADDR DO 0000 EN DISABLED Figure 15: Waveforms of Block RAM Data Operations with NO_CHANGE Selected Dedicated Multipliers All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to ...

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R Table 14: Embedded Multiplier Primitives Descriptions Signal Name Direction A[17:0] Input Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK. B[17:0] Input Apply the other 18-bit multiplicand ...

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Spartan-3 FPGA Family: Functional Description PSINCDEC PSEN PSCLK CLKIN CLKFB RST Figure 17: DCM Functional Blocks and Associated Signals The DCM has four functional Delay-Locked Loop (DLL), the Digital Frequency Synthe- sizer (DFS), the Phase Shifter (PS), and the Status ...

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R The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table 15. The clock outputs drive simulta- neously; however, the High Frequency ...

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Spartan-3 FPGA Family: Functional Description Table 16: DLL Attributes Attribute CLK_FEEDBACK DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2 CLKDV_DIVIDE DUTY_CYCLE_CORRECTION DLL Clock Input Connections An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG), which directly accesses the glo- bal clock ...

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R FPGA CLK90 BUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 CLK0 (a) On-Chip with CLK0 Feedback FPGA CLK90 IBUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 IBUFG CLK0 (c) Off-Chip with CLK0 Feedback Notes: 1. ...

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Spartan-3 FPGA Family: Functional Description Their relative timing in the Low Frequency Mode is shown in Figure 20. The CLK90, CLK180 and CLK270 outputs are not available when operating in the High Frequency mode. (See the description of the DLL_FREQUENCY_MODE ...

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R Digital Frequency Synthesizer (DFS) The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input and a ratio of two user-determined integers. Because of the wide range of possible ...

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Spartan-3 FPGA Family: Functional Description DFS Clock Output Connections There are two basic cases that determine how to connect the DFS clock outputs: on-chip and off-chip, which are illus- trated in Figure 19a and Figure 19c, respectively. This is similar ...

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R a. CLKOUT_PHASE_SHIFT = NONE b. CLKOUT_PHASE_SHIFT = FIXED Shift Range over all P Values: c. CLKOUT_PHASE_SHIFT = VARIABLE Shift Range over all P Values: Shift Range over all N Values: Notes represents the integer value ranging from ...

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Spartan-3 FPGA Family: Functional Description Table 20: Signals for Variable Phase Mode Signal Direction (1) PSEN Input Enables PSCLK for variable phase adjustment. (1) PSCLK Input Clock to synchronize phase shift adjustment. (1) PSINCDEC Input Chooses between increment and decrement ...

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R Table 22: DCM STATUS Bus Bit Name 0 Phase Shift A value of 1 indicates a phase shift overflow when one of two conditions occurs: Overflow • • 1 CLKIN Input A value of 1 indicates that the CLKIN ...

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Spartan-3 FPGA Family: Functional Description Table 24: BUFGMUX Select Mechanism S Input 0 1 The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a short setup ...

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R 4 DCM 4 DCM DS099-2 (v2.5) December 4, 2009 Product Specification GCLK6 GCLK4 GCLK5 GCLK7 4 4 BUFGMUX 4 • • • Horizontal Spine • • • BUFGMUX 4 GCLK3 GCLK1 GCLK2 GCLK0 Figure 22: ...

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Spartan-3 FPGA Family: Functional Description Interconnect Interconnect (or routing) passes signals among the various functional elements of Spartan-3 devices. There are four kinds of interconnect: Long lines, Hex lines, Double lines, and Direct lines. Long lines connect to one out ...

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... XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 The Dual-Purpose configuration pins comprise INIT_B, DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of these pins, according to its bank placement, uses the V lines for either Bank 4 (VCCO_4 on most packages, VCCO_BOTTOM on TQ144 and CP132 packages) or Bank www ...

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Spartan-3 FPGA Family: Functional Description 5 (VCCO_5). All the signals used in the serial configuration modes rely on VCCO_4 power. Signals used in the parallel configuration modes and Readback require from VCCO_5 as well as from VCCO_4. Both the Dedicated ...

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R 3.3V: XCF0xS 1.8V: XCFxxP V CCO V CCINT Platform Flash PROM XCF0xS or XCFxxP OE/RESET GND Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for ...

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Spartan-3 FPGA Family: Functional Description when operating in the User mode. This is accomplished by setting the Persist option to Yes. Multiple FPGAs can be configured using the Slave Parallel mode and can be made to start-up simultaneously. Figure 25 ...

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R Notes: 1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA to be configured in the chain shown above (or for the single FPGA ...

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Spartan-3 FPGA Family: Functional Description Figure 27: Configuration Flow Diagram for the Serial and Parallel Modes 50 54 Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 4 > 1V CCO ...

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R and V No (JTAG port becomes No Figure 28: Boundary-Scan Configuration Flow Diagram DS099-2 (v2.5) December 4, 2009 Product Specification Set PROG_B Low Power-On after Power-On V >1V CCINT and V > CCAUX Bank 4 > 1V ...

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Fam ily : Configuration is automatically initiated after power-on unless it is delayed by the ...

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R threshold levels (see Table 28, page plies reach their respective threshold, the POR reset is released and the FPGA begins its configuration process. Because the three supply inputs must be valid to release the POR reset and can be ...

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Spartan-3 FPGA Family: Functional Description Revision History Date Version No. 04/11/03 1.0 Initial Xilinx release 05/19/03 1.1 Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions. 07/11/03 1.2 Explained the configuration port Persist option in Figure 6 the same ...

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R DS099-3 (v2.5) December 4, 2009 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 27: Absolute Maximum Ratings (Continued) Symbol Description Input clamp current per I/O pin Electrostatic Discharge Voltage pins relative ESD to GND T Junction temperature J T Soldering temperature SOL ...

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... For information on power-on current needs, see 4. For mask revisions earlier than revision E (see and XC3S400 devices in QFP packages, and limited to 0.6 ms for the XC3S200, XC3S400, XC3S1500, and XC3S4000 devices in the FT and FG packages. 5. For earlier device versions with the FQ fabrication/process code (see 500 µ ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 31: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX ΔV (2) Voltage variance on ...

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R Table 32: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued) Symbol Description (3) R Equivalent resistance of pull-down resistor PD at User I/O, Dual-Purpose, and Dedicated pins, driven from I RPD R Value of external reference ...

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... XC3S4000 XC3S5000 XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 supply current XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 31. Quiescent supply current is measured with all I/O drivers of 25° CCINT = 3.465V, and V = 2.625V. The FPGA is programmed with a "blank" configuration ...

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R Table 34: Recommended Operating Conditions for User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) Min (V) Nom (V) (3) GTL - GTL_DCI - (3) GTLP - GTLP_DCI - HSLVDCI_15 1.4 HSLVDCI_18 1.7 HSLVDCI_25 2.3 HSLVDCI_33 3.0 HSTL_I, HSTL_I_DCI 1.4 ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 35: DC Characteristics of User I/Os Using Single-Ended Standards Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) GTL GTL_DCI GTLP GTLP_DCI HSLVDCI_15 HSLVDCI_18 HSLVDCI_25 HSLVDCI_33 HSTL_I HSTL_I_DCI HSTL_III HSTL_III_DCI HSTL_I_18 HSTL_I_DCI_18 HSTL_II_18 ...

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R Table 35: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Signal Standard (IOSTANDARD) and Current Drive Attribute (mA) (4) LVCMOS33 LVDCI_33, LVDCI_DV2_33 (4) LVTTL ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic V V GND level Table 36: Recommended Operating Conditions for User I/Os Using Differential Signal Standards Signal Standard (IOSTANDARD) Min (V) LDT_25 (ULVDS_25) 2.375 LVDS_25, LVDS_25_DCI 2.375 BLVDS_25 2.375 LVDSEXT_25, 2.375 ...

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R Internal Logic V OUTN V OUTP GND level Table 37: DC Characteristics of User I/Os Using Differential Signal Standards (1) Mask Signal Standard Revision LDT_25 (ULVDS_25) All LVDS_25 All ‘E’ (6) BLVDS_25 All LVDSEXT_25 All ‘E’ (6) LVPECL_25 All ...

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... Xilinx development software) and back-annotated to the simulation netlist. Table 38: Spartan-3 Speed Grade Designations (ISE v8.2i or later) Device Advance XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 www.xilinx.com R Preliminary Production –4, –5 (v1.37 and later) –4, –5 (v1.38 and later) DS099-3 (v2 ...

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... XC3S4000 1.94 2.24 XC3S5000 2.00 2.30 XC3S50 3.70 4.24 XC3S200 3.89 4.46 XC3S400 3.91 4.48 XC3S1000 4.00 4.59 XC3S1500 4.07 4.66 XC3S2000 4.19 4.80 XC3S4000 4.44 5.09 XC3S5000 4.38 5.02 and are based on the operating conditions set Table Units 46. ...

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... XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (3) LVCMOS25 , XC3S50 IOBDELAY = NONE, XC3S200 (4) with DCM XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (3) LVCMOS25 , XC3S50 IOBDELAY = IFD, XC3S200 without DCM XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set www.xilinx.com ...

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... XC3S50 -0.55 -0.55 XC3S200 -0.29 -0.29 XC3S400 -0.29 -0.29 XC3S1000 -0.55 -0.55 XC3S1500 -0.55 -0.55 XC3S2000 -0.55 -0.55 XC3S4000 -0.61 -0.61 XC3S5000 -0.68 -0.68 XC3S50 -2.74 -2.74 XC3S200 -3.00 -3.00 XC3S400 -2.90 -2.90 XC3S1000 -3.24 -3.24 XC3S1500 -3.55 -3.55 XC3S2000 -4 ...

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... IOBDELAY = NONE XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (2) LVCMOS25 , XC3S50 IOBDELAY = IFD XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Table 47 and are based on the operating conditions set forth Table 43. www.xilinx.com R Speed Grade -5 -4 Max Max Units 2.01 2.31 ns 1.50 1. ...

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R Table 43: Input Timing Adjustments for IOB Add the Adjustment Below Convert Input Time from LVCMOS25 to the Speed Grade Following Signal Standard (IOSTANDARD) -5 Single-Ended Standards GTL, GTL_DCI 0.44 GTLP, GTLP_DCI 0.36 HSLVDCI_15 0.51 HSLVDCI_18 0.29 HSLVDCI_25 0.51 ...

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... XC3S200 output drive, Fast slew rate XC3S400 XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 XC3S200 XC3S400 XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 (2) LVCMOS25 , 12mA XC3S200 output drive, Fast slew rate XC3S400 XC3S50 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 All Table 47 and are based on the operating conditions set Table 46 ...

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... Speed Grade -5 -4 Device Max Max Units All 0.74 0.85 ns All 0.72 0.82 ns XC3S200 7.71 8.87 ns XC3S400 XC3S50 8.38 9.63 ns XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 All 1.55 1.78 ns XC3S200 2.24 2.57 ns XC3S400 XC3S50 2.91 3.34 ns XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 46. 73 ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 46: Output Timing Adjustments for IOB Add the Adjust- Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards GTL GTL_DCI GTLP ...

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R Table 46: Output Timing Adjustments for IOB (Continued) Add the Adjust- Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS33 Slow ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test condi- tions. Table 47 presents the conditions to use for each stan- dard. The method ...

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R Table 47: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V REF LVCMOS18 - LVDCI_18 LVDCI_DV2_18 HSLVDCI_18 LVCMOS25 - LVDCI_25 LVDCI_DV2_25 HSLVDCI_25 LVCMOS33 - LVDCI_33 LVDCI_DV2_33 HSLVDCI_33 LVTTL - PCI33_3 Rising - Falling SSTL18_I 0.9 SSTL18_I_DCI ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 47: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V REF DIFF_SSTL2_II - DIFF_SSTL2_II_DCI Notes: 1. Descriptions of the relevant symbols are as follows: – V The reference voltage ...

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... XC3S1000 - - XC3S1500 - - XC3S2000 - - XC3S4000 - - XC3S5000 - - Notes: 1. The V lines for the pair of banks on each side of the CP132 and TQ144 packages are internally tied together. Each CCO pair of interconnected banks shares three V 2. The CP132, CPG132, FG1156, and FGG1156 packages are being discontinued and are not recommended for new designs ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 Single-Ended Standards GTL 0 0 GTL_DCI 0 0 GTLP 0 0 GTLP_DCI 0 ...

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R Table 49: Recommended Number of Simultaneously Switching Outputs per V -GND Pair (Continued) CCO Signal Standard VQ TQ (IOSTANDARD) 100 144 LVCMOS33 Slow ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Internal Logic Timing Table 50: CLB Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, CKO the time from the active transition at the CLK input to data appearing at ...

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R Table 51: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data SHCKO appearing on the distributed RAM output Setup Times T Setup time of data at the BX ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 53: Synchronous Multiplier Timing Symbol Description Clock-to-Output Times T When reading from the MULTCK Multiplier, the time from the active transition at the C clock input to data appearing ...

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R Table 55: Block RAM Timing Symbol Description Clock-to-Output Times T When reading from the Block BCKO RAM, the time from the active transition at the CLK input to data appearing at the DOUT output Setup Times T Time from ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Fre- quency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL ...

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... XC3S400 - 250 - 250 ± ± XC3S1000 - 400 - 400 ± ± XC3S1500 - 400 - 400 ± ± XC3S2000 - 400 - 400 ± ± XC3S4000 - 400 - 400 ± ± XC3S5000 - 400 - 400 ± ± All - 150 - 150 ± ± - 140 - 140 ± ± - 250 ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Table 58: Switching Characteristics for the DLL (Continued) Symbol Lock Time LOCK_DLL When using the DLL alone: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED ...

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... XC3S400 - 250 - ± ± XC3S1000 - 400 - ± ± XC3S1500 - 400 - ± ± XC3S2000 - 400 - ± ± XC3S4000 - 400 - ± ± XC3S5000 - 400 - ± ± All - 300 - All - 10.0 - 10.0 All - 10.0 - 10.0 Table 59. Mask and Fab Revisions, page 55 ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Phase Shifter (PS) Phase shifter operation is only supported if the DLL is in low-frequency mode, see software version 10.1.03 (or later). Table 61: Recommended Operating Conditions for the PS in Variable Phase ...

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R Miscellaneous DCM Timing Table 63: Miscellaneous DCM Timing Symbol DCM_INPUT_CLOCK_STOP Maximum duration that the CLKIN and CLKFB signals can be stopped DCM_RST_PW_MIN Minimum duration of a RST pulse width (3) DCM_RST_PW_MAX Maximum duration of a RST pulse width (4) ...

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... XC3S200 - 5 XC3S400 - 5 XC3S1000 - 5 XC3S1500 - 7 XC3S2000 - 7 XC3S4000 - 7 XC3S5000 - 7 All 0.3 - XC3S50 - 2 XC3S200 - 2 XC3S400 - 2 XC3S1000 - 2 XC3S1500 - 3 XC3S2000 - 3 XC3S4000 - 3 XC3S5000 - 3 All 250 - All 0.25 4.0 Table 31. This means power must be applied to all DS099-3 (v2.5) December 4, 2009 Product Specification R 1.2V 2.5V Units μ μs ...

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R PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 35: Waveforms for Master and Slave Serial Configuration Table 65: Timing for the Master and Slave Serial Configuration Modes Symbol Clock-to-Output Times T The time from the falling ...

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Spartan-3 FPGA Family: DC and Switching Characteristics PROG_B (Input) INIT_B (Open-Drain) CS_B (Input) RDWR_B (Input) CCLK (Input/Output (Inputs) High-Z BUSY (Output) Notes: 1. Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration. Figure 36: ...

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R Table 66: Timing for the Master and Slave Parallel Configuration Modes (Continued) Symbol Hold Times T The time from the rising transition at the CCLK pin to the point SMCCD when data is last held at the D0-D7 pins ...

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Spartan-3 FPGA Family: DC and Switching Characteristics TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 67: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the TCK pin to data ...

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... Updated timing parameters to match v1.37 speed file. All Spartan-3 part types, except XC3S5000, promoted to Production status. Removed V devices (Table 32). Added worst-case quiescent current values for XC3S2000, XC3S4000, XC3S5000 (Table 33). Added industrial temperature range specification and improved typical quiescent current values 18 MHz ...

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Spartan-3 FPGA Family: DC and Switching Characteristics Date Version No. 04/26/06 2.1 Updated document links. 05/25/07 2.2 Improved absolute maximum voltage specifications in allowance. Improved XC3S50 HBM ESD to 2000V in data, improved (reduced) the maximum quiescent current limits for ...

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R DS099-4 (v2.5) December 4, 2009 Introduction This data sheet module describes the various pins on a ® Spartan -3 FPGA and how they connect to the supported component packages. • The Pin Types section categorizes all of the FPGA ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 68: Types of Pins on Spartan-3 FPGAs (Continued) Type/ Color Code VREF Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins in the same bank, provides a reference ...

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R Table 69: Spartan-3 FPGA Pin Definitions Pin Name Direction I/O: General-purpose I/O pins I/O User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output I/O_Lxxy_# User-defined as input, output, bidirectional, three-state output, open-drain output, open-source output DUAL: Dual-purpose ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 FPGA Pin Definitions (Continued) Pin Name Direction IO_Lxxy_#/INIT_B Bidirectional (open-drain) during configuration User I/O after configuration DCI: Digitally Controlled Impedance reference resistor input pins IO_Lxxy_#/VRN_# or Input when using DCI IO/VRN_# Otherwise, ...

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R Table 69: Spartan-3 FPGA Pin Definitions (Continued) Pin Name Direction DONE Bidirectional with open-drain or totem-pole Output M0, M1, M2 Input HSWAP_EN Input JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during configuration, regardless of HSWAP_EN pin) ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 69: Spartan-3 FPGA Pin Definitions (Continued) Pin Name Direction VCCAUX: Auxiliary voltage supply pins VCCAUX Supply VCCINT: Internal core voltage supply pins VCCINT Supply GND: Ground supply pins GND Supply N.C.: Unconnected package pins ...

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R Bank 0 Bank 1 Bank 5 Bank 4 DUAL Type: Dual-Purpose Configuration and I/O Pins These pins serve dual purposes. The user-I/O pins are tem- porarily borrowed during the configuration process to load configuration data into the FPGA. After ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 70: Dual-Purpose Pins Used in Master or Slave Serial Mode Pin Name Direction DIN Input Serial Data Input: During the Master or Slave Serial configuration modes, DIN is the serial configuration data input, and ...

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R Assert Low both the chip-select pin, CS_B, and the read/write control pin, RDWR_B, to write the configuration data byte presented on the D0-D7 pins to the FPGA on a rising-edge of the configuration clock, CCLK. The order of CS_B ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 71: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Continued) Pin Name Direction RDWR_B Input Read/Write Control for Parallel Mode Configuration: In Master and Slave Parallel modes, assert this pin Low together with CS_B ...

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R One of eight I/O Banks User I/O User I/O (a) No termination DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires ...

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Spartan-3 FPGA Family: Pinout Descriptions CCLK: Configuration Clock The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an input-only pin for the Slave Serial and Slave Parallel config- uration modes. ...

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R Table 73: DonePin and DriveDone Bitstream Option Interaction Single- or Multi- DonePin DriveDone FPGA Design Pullnone No Single Pullnone No Pullnone Yes Single Pullnone Yes Pullup No Single Pullup No Pullup Yes Single Pullup Yes M2, M1, M0: Configuration ...

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... XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 49. XC3S2000 XC3S4000 XC3S5000 TDO Using JTAG Port After Configuration The JTAG port is always active and available before, during, and after FPGA configuration. Add the BSCAN_SPARTAN3 primitive to the design to create user-defined JTAG instruc- tions and JTAG chains to communicate with internal logic. ...

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R The TDO output can directly drive a 3.3V input but with reduced noise immunity. See 3.3V-Tolerant Configuration Interface, page 46 or XAPP453: The 3.3V Configuration of for additional details. Spartan-3 FPGAs The following interface precautions are recommended when connecting ...

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Spartan-3 FPGA Family: Pinout Descriptions VCCAUX Type: Voltage Supply for Auxiliary Logic The VCCAUX pins supply power to various auxiliary cir- cuits, such as to the Digital Clock Managers (DCMs), the JTAG pins, and to the dedicated configuration pins (CON- ...

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R Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> IO_Lxxy_#/ D5 IO_Lxxy_#/ D6 IO_Lxxy_#/ D7 IO_Lxxy_#/ CS_B IO_Lxxy_#/ RDWR_B IO_Lxxy_#/ DOUT (O) BUSY/DOUT DUAL: Dual-purpose configuration pins (INIT_B has a pull-up resistor to ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 78: Pin Behavior After Power-Up, During Configuration (Continued) Serial Modes Master Pin Name <0:0:0> M1 M1=0 (I) M0 M0=0 (I) HSWAP_EN HSWAP_EN (I) JTAG: JTAG interface pins (pull-up resistor to VCCAUX always active during ...

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R Bitstream Options Table 79 lists the various bitstream options that affect pins on a Spartan-3 FPGA. The table shows the names of the affected pins, describes the function of the bitstream option, Table 79: Bitstream Options Affecting Spartan-3 Pins ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 79: Bitstream Options Affecting Spartan-3 Pins (Continued) Affected Pin Name(s) M0 After configuration, this bitstream option either pulls M0 to VCCAUX via a pull-up resistor, to ground via a pull-down resistor, or allows M0 ...

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R Package Overview Table 80 shows the 10 low-cost, space-saving production package styles for the Spartan-3 family. Each package style is available as a standard and an environmentally-friendly lead-free (Pb-free) option. The Pb-free packages include an extra ‘G’ in the ...

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Spartan-3 FPGA Family: Pinout Descriptions Mechanical Drawings Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in Table 82. Table 82: Xilinx Package Mechanical Drawings Package VQ100 and VQG100 (1) CP132 and ...

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... XC3S1000 FG320 XC3S1500 FG320 XC3S400 FG456 XC3S1000 FG456 XC3S1500 FG456 XC3S2000 FG456 XC3S1000 FG676 XC3S1500 FG676 XC3S2000 FG676 XC3S4000 FG676 XC3S5000 FG676 XC3S2000 FG900 XC3S4000 FG900 XC3S5000 FG900 (1) XC3S4000 FG1156 (1) XC3S5000 FG1156 Notes: 1. The CP132, CPG132, FG1156, and FGG1156 packages are being discontinued and are not recommended for new designs. See http://www ...

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Spartan-3 FPGA Family: Pinout Descriptions Package Thermal Characteristics The power dissipated by an FPGA application has implica- tions on package selection and system design. The power consumed by a Spartan-3 FPGA is reported using either the XPower Estimator (XPE) or ...

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... FG(G)320 XC3S400 XC3S1000 XC3S1500 FG(G)456 XC3S400 XC3S1000 XC3S1500 XC3S2000 FG(G)676 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 FG(G)900 XC3S2000 XC3S4000 XC3S5000 (1) FG(G)1156 XC3S4000 XC3S5000 Notes: 1. The CP132, CPG132, FG1156, and FGG1156 packages are being discontinued and are not recommended for new designs. See http://www ...

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Spartan-3 FPGA Family: Pinout Descriptions VQ100: 100-lead Very-thin Quad Flat Package The XC3S50 and the XC3S200 devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices share a common footprint for this package as shown in Table ...

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R Table 86: VQ100 Package Pinout XC3S50 XC3S200 Bank Pin Name 7 IO_L23P_7 7 IO_L40N_7/VREF_7 7 IO_L40P_7 7 VCCO_7 N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A GND N/A ...

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Spartan-3 FPGA Family: Pinout Descriptions VQ100 Footprint IO_L01P_7/VRN_7 1 2 IO_L01N_7/VRP_7 GND 3 IO_L21P_7 4 IO_L21N_7 5 6 VCCO_7 7 VCCAUX IO_L23P_7 8 IO_L23N_7 9 10 GND IO_L40P_7 11 IO_L40N_7/VREF_7 12 IO_L40P_6/VREF_6 13 IO_L40N_6 14 IO_L24P_6 15 IO_L24N_6/VREF_6 16 17 ...

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R CP132: 132-Ball Chip-Scale Package Note: The CP132 and CPG132 packages are being discontinued and are not recommended for new designs. See inx.com/support/documentation/spartan-3.htm#19600 for the latest updates. The XC3S50 is available in the 132-ball chip-scale package, CP132. The pinout and ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 88: CP132 Package Pinout Bank XC3S50 Pin Name 6 IO_L20N_6 6 IO_L20P_6 6 IO_L22N_6 6 IO_L22P_6 6 IO_L23N_6 6 IO_L23P_6 6 IO_L24N_6/VREF_6 6 IO_L24P_6 6 IO_L40N_6 6 IO_L40P_6/VREF_6 7 IO_L01N_7/VRP_7 7 IO_L01P_7/VRN_7 7 IO_L21N_7 ...

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R User I/Os by Bank Table 89 indicates how the 89 available user-I/O pins are distributed between the eight I/O banks on the CP132 pack- Table 89: User I/Os Per Bank for XC3S50 in CP132 Package Package Edge I/O Bank ...

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Spartan-3 FPGA Family: Pinout Descriptions CP132 Footprint I/O VCCO_ A PROG_B TDI L01N_0 VRP_0 I/O I/O HSWAP_ B L01P_7 L01N_7 EN VRN_7 VRP_7 VCCO_ I/O C GND L01P_0 LEFT L21N_7 VRN_0 I/O I/O I/O D L22N_7 L22P_7 ...

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... R TQ144: 144-lead Thin Quad Flat Package The XC3S50, the XC3S200, and the XC3S400 are avail- able in the 144-lead thin quad flat package, TQ144. All devices share a common footprint for this package as shown in Table 90 and Figure 44. The TQ144 package only has four separate VCCO inputs, unlike the BGA packages, which have eight separate VCCO inputs ...

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... I/O VCCAUX P126 VCCO VCCAUX P138 VCCO VCCAUX P115 VCCO VCCAUX P106 VCCO VCCAUX P75 VCCO VCCAUX www.xilinx.com XC3S50 XC3S200 XC3S400 TQ144 Pin Pin Name Number VCCO_RIGHT P91 VCCO_BOTTOM P54 VCCO_BOTTOM P43 VCCO_BOTTOM P66 VCCO_LEFT P19 VCCO_LEFT P34 VCCO_LEFT P3 GND P136 ...

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R User I/Os by Bank Table 91 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the TQ144 pack- age. Table 91: User I/Os Per Bank in TQ144 Package Package Edge I/O Bank 0 ...

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Spartan-3 FPGA Family: Pinout Descriptions TQ144 Footprint IO_L01P_7/VRN_7 1 IO_L01N_7/VRP_7 2 X VCCO_LEFT 3 IO/VREF_7 4 IO_L20P_7 5 IO_L20N_7 6 IO_L21P_7 7 IO_L21N_7 8 GND 9 IO_L22P_7 10 IO_L22N_7 11 IO_L23P_7 12 IO_L23N_7 13 IO_L24P_7 14 IO_L24N_7 15 GND 16 ...

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... XC3S50 maps to a VREF-type pin on the XC3S200 and XC3S400. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C. pin on the XC3S50 to the same VREF voltage ...

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... IO_L28N_5/ P110 VCCO D6 P127 VCCO 5 IO_L28P_5/ P93 I/O D7 P97 I/O 5 IO_L31N_5/ P85 VREF D4 www.xilinx.com XC3S200 PQ208 XC3S50 XC3S400 Pin Pin Name Pin Name Number IO/VREF_4 P96 IO/VREF_4 P102 IO_L01N_4/ P101 VRP_4 IO_L01P_4/ P100 VRN_4 IO_L25N_4 P95 IO_L25P_4 P94 IO_L27N_4/ P92 DIN/D0 ...

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... P9 VREF N/A GND N/A GND P7 I/O N/A GND P11 I/O N/A GND P10 I/O www.xilinx.com XC3S200 PQ208 XC3S50 XC3S400 Pin Pin Name Pin Name Number IO_L21N_7 P13 IO_L21P_7 P12 IO_L22N_7 P16 IO_L22P_7 P15 IO_L23N_7 P19 IO_L23P_7 P18 IO_L24N_7 P21 IO_L24P_7 P20 ...

Page 138

... I/O banks for the XC3S50 in the P70 VCCINT PQ208 package. Similarly, P104 CONFIG able user-I/O pins are distributed between the eight I/O P103 CONFIG banks for the XC3S200 and XC3S400 in the PQ208 pack- age. All Possible I/O Pins by Type Maximum I/O I/O DUAL 15 9 ...

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... R Table 94: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package Package Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 DS099-4 (v2.5) December 4, 2009 Product Specification All Possible I/O Pins by Type Maximum I/O I/O DUAL www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions ...

Page 140

... I/O) I/O: Unrestricted, 72 general-purpose user I/O VREF: User I/O or input 16 voltage reference for bank N.C.: Unconnected pins for 17 XC3S50 ( ) XC3S200, XC3S400 (141 max user I/O) I/O: Unrestricted, 83 general-purpose user I/O VREF: User I/O or input 22 voltage reference for bank N.C.: No unconnected pins 0 ...

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R Bank 1 Bank 4 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions IO_L01N_2/VRP_2 156 IO_L01P_2/VRN_2 155 IO/VREF_2 ( ) 154 VCCO_2 153 IO_L19N_2 152 GND 151 IO_L19P_2 150 IO_L20N_2 149 IO_L20P_2 148 IO_L21N_2 147 IO_L21P_2 ...

Page 142

... FT256: 256-lead Fine-pitch Thin Ball Grid Array The 256-lead fine-pitch thin ball grid array package, FT256, supports three different Spartan-3 devices, including the XC3S200, the XC3S400, and the XC3S1000. The footprints for all three devices are identical, as shown in Figure 46. All the package pins appear in Table 95 bank number, then by pin name ...

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... T12 I/O 5 T14 I/O 5 N12 VREF 5 P13 VREF 5 T10 VREF 5 R13 DCI 5 T13 DCI www.xilinx.com XC3S200 XC3S400 FT256 XC3S1000 Pin Pin Name Number IO_L25N_4 P12 IO_L25P_4 R12 IO_L27N_4/DIN/D0 M11 IO_L27P_4/D1 N11 IO_L28N_4 P11 IO_L28P_4 R11 IO_L29N_4 M10 IO_L29P_4 N10 IO_L30N_4/D2 P10 ...

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... N/A C3 VREF N/A D1 I/O N/A D2 I/O N/A E3 VREF N/A D3 I/O N/A E1 I/O N/A E2 I/O N/A F4 I/O N/A E4 I/O N/A www.xilinx.com XC3S200 XC3S400 FT256 XC3S1000 Pin Pin Name Number IO_L22N_7 F2 IO_L22P_7 F3 IO_L23N_7 G5 IO_L23P_7 F5 IO_L24N_7 G3 IO_L24P_7 G4 IO_L39N_7 H3 IO_L39P_7 H4 IO_L40N_7/VREF_7 H1 IO_L40P_7 G1 VCCO_7 G6 VCCO_7 H5 VCCO_7 ...

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... All Possible I/O Pins by Type Maximum I/O I/O DUAL www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions XC3S200 XC3S400 FT256 XC3S1000 Pin Pin Name Number VCCINT M12 VCCINT N4 VCCINT N13 T15 R14 C14 A2 A15 C13 indicates how the available user-I/O pins are dis- DCI VREF ...

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Spartan-3 FPGA Family: Pinout Descriptions FT256 Footprint I TDI GND L01P_0 VREF_0 VRN_0 I/O I/O B PROG_B L01P_7 GND L01N_0 VRN_7 VRP_0 I/O I/O I/O HSWAP_ C L01N_7 L16P_7 L16N_7 EN VRP_7 VREF_7 I/O ...

Page 147

... FG320: 320-lead Fine-pitch Ball Grid Array The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3 devices, including the XC3S400, the XC3S1000, and the XC3S1500. The footprint for all three devices is identical, as shown in Figure 47. The FG320 package array of solder balls minus the four center balls ...

Page 148

... I/O 4 P15 I/O 4 N15 I/O 4 M14 I/O 4 N14 I/O 4 M15 I/O 4 M16 VREF 4 M18 I/O www.xilinx.com XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number IO_L24P_3 N17 IO_L27N_3 L14 IO_L27P_3 L13 IO_L34N_3 L15 IO_L34P_3/VREF_3 L16 IO_L35N_3 L18 IO_L35P_3 L17 IO_L39N_3 K13 IO_L39P_3 ...

Page 149

... U8 VCCO DCI 7 T2 DCI VREF I/O 7 www.xilinx.com Spartan-3 FPGA Family: Pinout Descriptions XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number IO_L20P_6 P1 IO_L21N_6 N4 IO_L21P_6 P4 IO_L22N_6 N5 IO_L22P_6 M5 IO_L23N_6 M3 IO_L23P_6 M4 IO_L24N_6/VREF_6 N2 IO_L24P_6 M1 IO_L27N_6 L6 IO_L27P_6 L5 IO_L34N_6/VREF_6 L3 IO_L34P_6 L4 IO_L35N_6 L2 IO_L35P_6 ...

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... L10 GND VCCAUX TCK L11 GND VCCAUX TDI L8 GND VCCAUX TDO L9 GND VCCAUX TMS M12 GND M7 GND N1 GND N18 GND www.xilinx.com XC3S400 XC3S1000 FG320 XC3S1500 Pin Pin Name Number GND T10 GND T9 GND U17 GND U2 GND V1 GND V13 GND V18 GND ...

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R User I/Os by Bank Table 98 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks on the FG320 pack- age. Table 98: User I/Os Per Bank in FG320 Package Maximum Package Edge I/O Bank ...

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Spartan-3 FPGA Family: Pinout Descriptions FG320 Footprint Bank I/O I/O I/O I/O A GND L01N_0 L01P_0 L15N_0 L15P_0 VRP_0 VRN_0 I/O I/O I/O I/O B GND L16P_7 VREF_0 L09N_0 L25N_0 VREF_7 I/O I/O I/O ...

Page 153

... XC3S2000. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C. pin on the XC3S400 to the same VREF voltage. This provides maximum flexibility as you could potentially migrate a design from the XC3S400 device to an XC3S1000, an XC3S1500 XC3S2000 FPGA without changing the printed circuit board ...

Page 154

Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 1 IO/VREF_1 IO/VREF_1 1 N. IO/VREF_1 1 IO_L01N_1/ IO_L01N_1/ VRP_1 VRP_1 1 IO_L01P_1/ IO_L01P_1/ VRN_1 VRN_1 1 IO_L06N_1/ ...

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R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 2 IO_L40P_2/ IO_L40P_2/ VREF_2 VREF_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 ...

Page 156

Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 4 IO_L24P_4 IO_L24P_4 4 IO_L25N_4 IO_L25N_4 4 IO_L25P_4 IO_L25P_4 4 IO_L27N_4/ IO_L27N_4/ DIN/D0 DIN/D0 4 IO_L27P_4/ IO_L27P_4 ...

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R Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 6 IO_L19N_6 IO_L19N_6 6 IO_L19P_6 IO_L19P_6 6 IO_L20N_6 IO_L20N_6 6 IO_L20P_6 IO_L20P_6 6 IO_L21N_6 IO_L21N_6 6 IO_L21P_6 IO_L21P_6 6 IO_L22N_6 IO_L22N_6 6 IO_L22P_6 IO_L22P_6 ...

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Spartan-3 FPGA Family: Pinout Descriptions Table 99: FG456 Package Pinout (Continued) 3S1000 3S1500 3S400 3S2000 Bank Pin Name Pin Name 7 IO_L40N_7/ IO_L40N_7/ VREF_7 VREF_7 7 IO_L40P_7 IO_L40P_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 7 VCCO_7 VCCO_7 ...

Page 159

... User I/Os by Bank Table 100 indicates how the available user-I/O pins are dis- tributed between the eight I/O banks for the XC3S400 in the FG456 package. Similarly, Table 101 Table 100: User I/Os Per Bank for XC3S400 in FG456 Package I/O Maximum Edge Bank 0 ...

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... I/O) I/O: Unrestricted, 196 general-purpose user I/O VREF: User I/O or input 32 voltage reference for bank N.C.: Unconnected pins for 69 XC3S400 ( ) XC3S1000, XC3S1500, XC3S2000 (333 max user I/O) I/O: Unrestricted, 261 general-purpose user I/O VREF: User I/O or input 36 voltage reference for bank N ...

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R Bank I/O I/O I/O I/O L22N_1 I/O VCCAUX L30N_1 L28N_1 L25P_1 I/O I/O I/O I/O I/O I/O L22P_1 L32N_1 L30P_1 L28P_1 L25N_1 L16N_1 GCLK5 I/O I/O I/O I/O L19N_1 L32P_1 GND VCCO_1 ...

Page 162

... XC3S1000 or XC3S1500 that maps to a user-I/O pin on the XC3S2000, XC3S4000, and XC3S5000. If the table entry is shaded tan, then the unconnected pin on either the XC3S1000 or XC3S1500 maps to a VREF-type pin on the XC3S2000, XC3S4000, and XC3S5000 ...

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... VCCO_0 0 VCCO_0 VCCO_0 0 VCCO_0 VCCO_0 0 VCCO_0 VCCO_0 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions XC3S2000 XC3S4000 Pin Name Pin Name IO_L11N_0 IO_L11N_0 IO_L11P_0 IO_L11P_0 IO_L12N_0 IO_L12N_0 IO_L12P_0 IO_L12P_0 IO_L15N_0 IO_L15N_0 IO_L15P_0 IO_L15P_0 IO_L16N_0 IO_L16N_0 IO_L16P_0 IO_L16P_0 IO_L17N_0 ...

Page 164

... IO_L19P_1 1 IO_L22N_1 IO_L22N_1 1 IO_L22P_1 IO_L22P_1 1 N. IO_L23N_1 1 N. IO_L23P_1 1 IO_L24N_1 IO_L24N_1 1 IO_L24P_1 IO_L24P_1 1 IO_L25N_1 IO_L25N_1 1 IO_L25P_1 IO_L25P_1 1 N. IO_L26N_1 164 XC3S2000 XC3S4000 Pin Name Pin Name IO/VREF_1 IO/VREF_1 IO/VREF_1 IO/VREF_1 IO/VREF_1 IO/VREF_1 IO_L01N_1/VRP_1 IO_L01N_1/VRP_1 IO_L01P_1/VRN_1 IO_L01P_1/VRN_1 IO_L04N_1 IO_L04N_1 IO_L04P_1 IO_L04P_1 IO_L05N_1 ...

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... IO_L14P_2 2 IO_L16N_2 IO_L16N_2 2 IO_L16P_2 IO_L16P_2 2 IO_L17N_2 IO_L17N_2 2 IO_L17P_2/VREF_2 IO_L17P_2/VREF_2 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions XC3S2000 XC3S4000 Pin Name Pin Name IO_L26P_1 IO_L26P_1 IO_L27N_1 IO_L27N_1 IO_L27P_1 IO_L27P_1 IO_L28N_1 IO_L28N_1 IO_L28P_1 IO_L28P_1 IO_L29N_1 IO_L29N_1 IO_L29P_1 IO_L29P_1 IO_L30N_1 ...

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... VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 2 VCCO_2 VCCO_2 3 IO_L01N_3/VRP_3 IO_L01N_3/VRP_3 3 IO_L01P_3/VRN_3 IO_L01P_3/VRN_3 166 XC3S2000 XC3S4000 Pin Name Pin Name IO_L19N_2 IO_L19N_2 IO_L19P_2 IO_L19P_2 IO_L20N_2 IO_L20N_2 IO_L20P_2 IO_L20P_2 IO_L21N_2 IO_L21N_2 IO_L21P_2 IO_L21P_2 IO_L22N_2 IO_L22N_2 IO_L22P_2 IO_L22P_2 IO_L23N_2/VREF_2 IO_L23N_2/VREF_2 IO_L23P_2 IO_L23P_2 ...

Page 167

... IO_L29P_3 3 IO_L31N_3 IO_L31N_3 3 IO_L31P_3 IO_L31P_3 3 IO_L32N_3 IO_L32N_3 3 IO_L32P_3 IO_L32P_3 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions XC3S2000 XC3S4000 Pin Name Pin Name IO_L02N_3/VREF_3 IO_L02N_3/VREF_3 IO_L02P_3 IO_L02P_3 IO_L03N_3 IO_L03N_3 IO_L03P_3 IO_L03P_3 IO_L05N_3 IO_L05N_3 IO_L05P_3 IO_L05P_3 IO_L06N_3 IO_L06N_3 IO_L06P_3 ...

Page 168

... IO_L07N_4 IO_L07N_4 4 IO_L07P_4 IO_L07P_4 4 IO_L08N_4 IO_L08N_4 4 IO_L08P_4 IO_L08P_4 4 IO_L09N_4 IO_L09N_4 4 IO_L09P_4 IO_L09P_4 4 IO_L10N_4 IO_L10N_4 168 XC3S2000 XC3S4000 Pin Name Pin Name IO_L33N_3 IO_L33N_3 IO_L33P_3 IO_L33P_3 IO_L34N_3 IO_L34N_3 IO_L34P_3/VREF_3 IO_L34P_3/VREF_3 IO_L35N_3 IO_L35N_3 IO_L35P_3 IO_L35P_3 IO_L38N_3 IO_L38N_3 IO_L38P_3 IO_L38P_3 IO_L39N_3 IO_L39N_3 IO_L39P_3 IO_L39P_3 ...

Page 169

... VCCO_4 VCCO_4 4 VCCO_4 VCCO_4 4 VCCO_4 VCCO_4 4 VCCO_4 VCCO_4 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions XC3S2000 XC3S4000 Pin Name Pin Name IO_L10P_4 IO_L10P_4 IO_L11N_4 IO_L11N_4 IO_L11P_4 IO_L11P_4 IO_L12N_4 IO_L12N_4 IO_L12P_4 IO_L12P_4 IO_L15N_4 IO_L15N_4 IO_L15P_4 IO_L15P_4 IO_L16N_4 IO_L16N_4 ...

Page 170

... IO_L19N_5 IO_L19N_5 5 IO_L19P_5/VREF_5 IO_L19P_5/VREF_5 5 IO_L22N_5 IO_L22N_5 5 IO_L22P_5 IO_L22P_5 5 N. IO_L23N_5 5 N. IO_L23P_5 5 IO_L24N_5 IO_L24N_5 5 IO_L24P_5 IO_L24P_5 5 IO_L25N_5 IO_L25N_5 5 IO_L25P_5 IO_L25P_5 170 XC3S2000 XC3S4000 Pin Name Pin Name IO/VREF_5 IO/VREF_5 IO/VREF_5 IO/VREF_5 IO_L01N_5/ IO_L01N_5/ RDWR_B RDWR_B IO_L01P_5/CS_B IO_L01P_5/CS_B IO_L04N_5 IO_L04N_5 IO_L04P_5 IO_L04P_5 ...

Page 171

... IO_L14N_6 6 IO_L14P_6 IO_L14P_6 6 IO_L16N_6 IO_L16N_6 6 IO_L16P_6 IO_L16P_6 6 IO_L17N_6 IO_L17N_6 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions XC3S2000 XC3S4000 Pin Name Pin Name IO_L26N_5 IO_L26N_5 IO_L26P_5 IO_L26P_5 IO_L27N_5/VREF_5 IO_L27N_5/VREF_5 IO_L27P_5 IO_L27P_5 IO_L28N_5/D6 IO_L28N_5/D6 IO_L28P_5/D7 IO_L28P_5/D7 IO_L29N_5 IO_L29N_5 IO_L29P_5/VREF_5 ...

Page 172

... VCCO_6 VCCO_6 6 VCCO_6 VCCO_6 6 VCCO_6 VCCO_6 6 VCCO_6 VCCO_6 6 VCCO_6 VCCO_6 6 VCCO_6 VCCO_6 7 IO_L01N_7/VRP_7 IO_L01N_7/VRP_7 172 XC3S2000 XC3S4000 Pin Name Pin Name IO_L17P_6/VREF_6 IO_L17P_6/VREF_6 IO_L19N_6 IO_L19N_6 IO_L19P_6 IO_L19P_6 IO_L20N_6 IO_L20N_6 IO_L20P_6 IO_L20P_6 IO_L21N_6 IO_L21N_6 IO_L21P_6 IO_L21P_6 IO_L22N_6 IO_L22N_6 IO_L22P_6 IO_L22P_6 IO_L23N_6 IO_L23N_6 ...

Page 173

... IO_L29N_7 7 IO_L29P_7 IO_L29P_7 7 IO_L31N_7 IO_L31N_7 7 IO_L31P_7 IO_L31P_7 7 IO_L32N_7 IO_L32N_7 DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions XC3S2000 XC3S4000 Pin Name Pin Name IO_L01P_7/VRN_7 IO_L01P_7/VRN_7 IO_L02N_7 IO_L02N_7 IO_L02P_7 IO_L02P_7 IO_L03N_7/VREF_7 IO_L03N_7/VREF_7 IO_L03P_7 IO_L03P_7 IO_L05N_7 IO_L05N_7 IO_L05P_7 IO_L05P_7 IO_L06N_7 ...

Page 174

... GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND N/A GND GND 174 XC3S2000 XC3S4000 Pin Name Pin Name IO_L32P_7 IO_L32P_7 IO_L33N_7 IO_L33N_7 IO_L33P_7 IO_L33P_7 IO_L34N_7 IO_L34N_7 IO_L34P_7 IO_L34P_7 IO_L35N_7 IO_L35N_7 IO_L35P_7 IO_L35P_7 IO_L38N_7 IO_L38N_7 IO_L38P_7 ...

Page 175

... GND GND N/A GND GND N/A GND GND N/A GND GND DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions XC3S2000 XC3S4000 Pin Name Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND ...

Page 176

... VCCINT VCCINT N/A VCCINT VCCINT VCC CCLK CCLK AUX VCC DONE DONE AUX VCC HSWAP_EN HSWAP_EN AUX 176 XC3S2000 XC3S4000 Pin Name Pin Name GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX ...

Page 177

... XC3S4000 is pin compatible with XC3S2000 but uses alternate differential pair labeling on six package balls (H20, H21, H22, H23, H24, J21). 3. XC3S5000 is pin compatible with XC3S4000 but uses alternate differential pair functionality on fifteen package balls (A3, A8, B8, B18, C4, C8, C18, D8, D18, E8, E18, H23, H24, AB9, and AC9). ...

Page 178

... Table 104: User I/Os Per Bank for XC3S1500 in FG676 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 Table 105: User I/Os Per Bank for XC3S2000, XC3S4000, and XC3S5000 in FG676 Package Maximum Edge I/O Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 178 ...

Page 179

R DS099-4 (v2.5) December 4, 2009 Product Specification Spartan-3 FPGA Family: Pinout Descriptions www.xilinx.com 179 ...

Page 180

... I/O: Unrestricted, 403 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: Unconnected pins for 2 XC3S1500 ( ) XC3S2000, XC3S4000, XC3S5000 (489 max user I/O) I/O: Unrestricted, 405 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: No unconnected pins ...

Page 181

... Spartan-3 FPGA Family: Pinout Descriptions Right Half of Package (top view Notes: 1. Differential pair assignments shown in parentheses on J balls H20, H21, H22, H23, H24, and J21 are for K XC3S4000 only. 2. Differential pair assignments for the XC3S5000 are L different on 15 balls (see Table 102 for details ...

Page 182

... Table 106. If the table entry is shaded, then there is an unconnected pin on the XC3S2000 that maps to a user-I/O pin on the XC3S4000 and XC3S5000. An electronic version of this package pinout table and foot- print diagram is available for download from the Xilinx web- site at http://www ...

Page 183

... VREF 1 IO_L21N_1 A27 DCI 1 IO_L21P_1 1 IO_L22N_1 B27 DCI 1 IO_L22P_1 1 IO_L23N_1 D26 I/O 1 IO_L23P_1 C27 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L03N_1 A26 IO_L03P_1 B26 IO_L04N_1 B25 IO_L04P_1 C25 IO_L05N_1 F24 IO_L05P_1 F25 IO_L06N_1/ C24 VREF_1 ...

Page 184

... I/O 2 IO_L24N_2 C29 DCI 2 IO_L24P_2 C30 DCI 2 IO_L26N_2 2 IO_L26P_2 D27 I/O 2 IO_L27N_2 D28 I/O 2 IO_L27P_2 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L03N_2/ D29 VREF_2 IO_L03P_2 D30 IO_L04N_2 E29 IO_L04P_2 E30 IO_L05N_2 F28 IO_L05P_2 F29 IO_L06N_2 G27 ...

Page 185

... IO_L20N_3 G26 VCCO 3 IO_L20P_3 E28 VCCO 3 IO_L21N_3 J28 VCCO 3 IO_L21P_3 N28 VCCO 3 IO_L22N_3 AB25 I/O 3 IO_L22P_3 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L01N_3/ AH30 VRP_3 IO_L01P_3/ AH29 VRN_3 IO_L02N_3/ AG28 VREF_3 IO_L02P_3 AG27 IO_L03N_3 AG30 IO_L03P_3 ...

Page 186

... IO_L12N_4 V26 I/O 4 IO_L12P_4 U20 VCCO 4 IO_L13N_4 V20 VCCO 4 IO_L13P_4 W20 VCCO 4 IO_L14N_4 Y22 VCCO 4 IO_L14P_4 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number VCCO_3 V24 VCCO_3 AB24 VCCO_3 AD26 VCCO_3 V28 VCCO_3 AB28 VCCO_3 AF28 IO AA16 IO AG18 ...

Page 187

... DUAL 5 IO_L07N_5 AH16 DUAL 5 IO_L07P_5 5 IO_L08N_5 AJ16 GCLK 5 IO_L08P_5 5 IO_L09N_5 AK16 GCLK 5 IO_L09P_5 AH25 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L33P_4 AJ25 IO_L34N_4 AE25 IO_L34P_4 AE24 IO_L35N_4 AG24 IO_L35P_4 AH24 IO_L38N_4 AJ24 IO_L38P_4 AK24 VCCO_4 ...

Page 188

... VREF 6 IO_L03P_6 6 IO_L04N_6 AE13 I/O 6 IO_L04P_6 AJ14 DUAL 6 IO_L05N_6 6 IO_L05P_6 AH14 DUAL 6 IO_L06N_6 6 IO_L06P_6 AC15 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L29P_5/ AB15 VREF_5 IO_L30N_5 AD15 IO_L30P_5 AD14 IO_L31N_5/ AG15 D4 IO_L31P_5/ AF15 D5 IO_L32N_5/ AJ15 GCLK3 ...

Page 189

... I/O VRP_7 W3 I/O 7 IO_L01P_7/ W2 I/O VRN_7 W1 I/O 7 IO_L02N_7 W10 I/O 7 IO_L02P_7 V10 I/O 7 IO_L03N_7/ VREF_7 V9 I/O 7 IO_L03P_7 V8 I/O www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L31N_6 W5 IO_L31P_6 V6 IO_L32N_6 V5 IO_L32P_6 V4 IO_L33N_6 V2 IO_L33P_6 V1 IO_L34N_6/ U10 VREF_6 IO_L34P_6 U9 IO_L35N_6 U7 IO_L35P_6 U6 ...

Page 190

... I/O 7 VCCO_7 L1 I/O 7 VCCO_7 L2 I/O 7 VCCO_7 M6 I/O 7 VCCO_7 M7 I/O 7 VCCO_7 M3 I/O N/A GND M4 I/O N/A GND www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number IO_L27N_7 M1 IO_L27P_7/ M2 VREF_7 IO_L28N_7 N10 IO_L28P_7 M10 IO_L29N_7 N8 IO_L29P_7 N9 IO_L31N_7 N1 IO_L31P_7 N2 IO_L32N_7 P9 IO_L32P_7 P10 ...

Page 191

... N/A GND P14 GND N/A GND R14 GND N/A GND T14 GND N/A GND U14 GND N/A GND www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number GND V14 GND AC14 GND AF14 GND AK14 GND M15 GND N15 ...

Page 192

... VCCAUX VCCAUX CCLK D17 VCCAUX VCCAUX DONE AG17 VCCAUX VCCAUX HSWAP_EN D21 VCCAUX VCCAUX M0 AG21 VCCAUX VCCAUX M1 D25 VCCAUX VCCAUX M2 www.xilinx.com XC3S4000 FG900 XC3S2000 XC3S5000 Pin Pin Name Pin Name Number VCCAUX AG25 VCCAUX F27 VCCAUX K27 VCCAUX P27 VCCAUX U27 ...

Page 193

... Table 107: User I/Os Per Bank for XC3S2000 in FG900 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 Table 108: User I/Os Per Bank for XC3S4000 and XC3S5000 in FG900 Package I/O Maximum Edge Bank 0 Top 1 2 Right 3 4 Bottom 5 6 Left 7 DS099-4 (v2 ...

Page 194

... I/O: Unrestricted, 481 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: Unconnected pins for 68 XC3S2000 ( ) XC3S4000, XC3S5000 (633 max user I/O) I/O: Unrestricted, 549 general-purpose user I/O VREF: User I/O or input 48 voltage reference for bank N.C.: No unconnected pins ...

Page 195

R Bank I/O I/O I/O I/O L39N_1 I/O GND GND L26N_1 L21N_1 L15N_1 L11N_1 I/O I/O I/O I/O I/O I/O I/O L39P_1 L32N_1 L17N_1 L28N_1 L26P_1 L21P_1 L15P_1 L11P_1 VREF_1 GCLK5 I/O ...

Page 196

... XC3S5000. If the table entry is shaded tan, which only occurs on ball L29 in I/O Bank 2, then the unconnected pin on the XC3S4000 maps to a VREF-type pin on the XC3S5000. If the other VREF_2 pins all connect to a volt- age reference to support a special I/O standard, then also connect the N ...

Page 197

... N. A17 GCLK I I/O 1 IO/VREF_1 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L36N_0 B8 IO_L36P_0 A8 IO_L37N_0 D10 IO_L37P_0 C10 IO_L38N_0 B10 IO_L38P_0 A10 IO_L39N_0 G11 IO_L39P_0 F11 IO_L40N_0 B11 IO_L40P_0 A11 VCCO_0 B13 VCCO_0 C4 VCCO_0 C8 VCCO_0 ...

Page 198

... I K23 I F23 VREF G23 I/O 1 IO_L37N_1 D23 I/O 1 IO_L37P_1 www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L18P_1 E23 IO_L19N_1 A23 IO_L19P_1 B23 IO_L20N_1 K22 IO_L20P_1 L22 IO_L21N_1 G22 IO_L21P_1 H22 IO_L22N_1 C22 IO_L22P_1 ...

Page 199

... IO_L27P_2 H30 I/O 2 IO_L28N_2 H33 I/O 2 IO_L28P_2 H34 I/O 2 IO_L29N_2 J28 I/O 2 IO_L29P_2 J29 I/O www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number IO_L09N_2/ H31 VREF_2 IO_L09P_2 J31 IO_L10N_2 J32 IO_L10P_2 J33 IO_L11N_2 J27 IO_L11P_2 K26 IO_L12N_2 K27 IO_L12P_2 ...

Page 200

... IO_L10N_3 P28 I/O 3 IO_L10P_3 T24 I/O 3 IO_L11N_3 U24 I/O 3 IO_L11P_3 D32 VCCO 3 IO_L12N_3 H28 VCCO www.xilinx.com FG1156 XC3S4000 XC3S5000 Pin Pin Name Pin Name Number VCCO_2 H32 VCCO_2 L27 VCCO_2 L31 VCCO_2 N23 VCCO_2 N29 VCCO_2 N33 VCCO_2 P23 VCCO_2 R23 ...