XC3S1600E-4FG400I Xilinx Inc, XC3S1600E-4FG400I Datasheet - Page 98
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XC3S1600E-4FG400I
Manufacturer Part Number
XC3S1600E-4FG400I
Description
IC FPGA SPARTAN 3E 400FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-4FG400I
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
304
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
400-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Functional Description
Slave Serial Mode
For additional information, refer to the “Slave Serial Mode”
chapter in UG332.
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
such as a microprocessor or microcontroller writes serial
configuration data into the FPGA, using the synchronous
serial interface shown in
data is presented on the FPGA’s DIN input pin with suffi-
cient setup time before each rising edge of the externally
generated CCLK clock input.
98
•
•
•
•
Internal memory
Disk drive
Over network
Over RF link
Configuration
Memory
Source
Download Host
Intelligent
Recommend
open-drain
PROG_B
•
•
•
READ/WRITE
Microcontroller
Processor
Tester
driver
DATA[7:0]
VCC
GND
PROG_B
SELECT
V
CLOCK
INIT_B
TMS
TCK
TDO
DONE
BUSY
TDI
JTAG
2.5V
Figure
63. The serial configuration
Figure 62: Daisy-Chaining using Slave Parallel Mode
Parallel
Slave
Mode
‘1’
‘1’
‘0’
‘0’
P
HSWAP
M2
M1
M0
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
TDI
TMS
TCK
PROG_B
Spartan-3E
VCCINT
+1.2V
FPGA
GND
VCCAUX
VCCO_0
VCCO_1
VCCO_2
www.xilinx.com
CSO_B
INIT_B
DONE
LDC0
LDC1
LDC2
HDC
TDO
VCCO_0
VCCO_1
+2.5V
V
V
The intelligent host starts the configuration process by puls-
ing PROG_B and monitoring that the INIT_B pin goes High,
indicating that the FPGA is ready to receive its first data.
The host then continues supplying data and clock signals
until either the DONE pin goes High, indicating a successful
configuration, or until the INIT_B pin goes Low, indicating a
configuration error. The configuration process requires
more clock cycles than indicated from the configuration file
size. Additional clocks are required during the FPGA’s
start-up sequence, especially if the FPGA is programmed to
wait for selected Digital Clock Managers (DCMs) to lock to
their respective clock inputs (see
+2.5V
Parallel
Slave
Mode
‘0’
P
‘1’
‘1’
‘0’
HSWAP
M2
M1
M0
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
TDI
TMS
TCK
PROG_B
Spartan-3E
VCCINT
FPGA
+1.2V
GND
DS312-2 (v3.8) August 26, 2009
VCCAUX
VCCO_0
VCCO_1
VCCO_2
Start-Up, page
CSO_B
INIT_B
DONE
LDC0
LDC1
LDC2
HDC
TDO
Product Specification
VCCO_0
VCCO_1
+2.5V
V
DS312-2_53_082009
107).
D[7:0]
CCLK
CSO_B
PROG_B
DONE
INIT_B
TMS
TCK
R
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