M0516ZAN Nuvoton Technology Corporation of America, M0516ZAN Datasheet - Page 251

• Manufacturer Part Number: M0516ZAN
• Description: IC MCU 32BIT 64KB FLASH 33QFN
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M0516ZAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 33-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

NuMicro M051
[2]
[1]
[0]
SS_LVL
Reserved
SSR
™
Series Technical Reference Manual
1 = If this bit is set, SPISS0/1 signal is generated automatically. It means that
device/slave select signal, which is set in SSR[0] register is asserted by the SPI
controller when transmit/receive is started by setting GO_BUSY, and is de-
asserted after each transmit/receive is finished.
Slave Select Active Level
It defines the active level of slave select signal (SPISS0/1).
0 = The slave select signal SPISS0/1 is active at low-level/falling-edge.
1 = The slave select signal SPISS0/1 is active at high-level/rising-edge.
Reserved
Slave Select Register (Master only)
If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to an active
state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 1 to this bit will select the SPISSx line to be
automatically driven to active state for the duration of the transmit/receive, and
will be driven to inactive state for the rest of the time. (The active level of
SPISSx is specified in SS_LVL).
Note: SPISSx is always defined as device/slave select input signal in slave
mode.
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Publication Release Date: Sept 14, 2010
Revision V1.2