AT89LP52-20PU Atmel, AT89LP52-20PU Datasheet - Page 74

IC MCU 8051 8K FLASH SPI 40PDIP

AT89LP52-20PU

Manufacturer Part Number
AT89LP52-20PU
Description
IC MCU 8051 8K FLASH SPI 40PDIP
Manufacturer
Atmel
Series
89LPr
Datasheet

Specifications of AT89LP52-20PU

Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
36
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Table 15-2.
Note:
Table 15-3.
74
WDTCON Address = A7H
Not Bit Addressable
Bit
Symbol
PS2
PS1
PS0
WDIDLE
DISRTO
SWRST
WDTOVF
WDTEN
WDTCON Address = A6H
Not Bit Addressable
Bit
The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading
the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to
WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST.
1. WDTCON.4 and WDTCON.3 function as WDIDLE and DISRTO only in Fast mode. In Compatibility mode these bits are in
AT89LP51/52 - Preliminary
PS2
AUXR. (See
7
7
Function
Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal
period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.
WDT Disable during Idle
halts counting in Idle mode.
Disable Reset Output
When DISRTO = 1 the reset pin is input only.
Software Reset Flag. Set when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set
when an incorrect sequence is written to WDTRST. Must be cleared by software.
Watchdog Overflow Flag. Set when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect
sequence is written to WDTRST. Must be cleared by software.
Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The
WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST
WDTCON – Watchdog Control Register
WDTRST – Watchdog Reset Register
Table 3-3 on page
PS1
6
6
(1)
. When DISTRO = 0 the reset pin is driven to the same level as POL when the WDT resets.
(1)
. When WDIDLE = 0 the WDT continues to count in Idle mode. When WDIDLE = 1 the WDT
PS0
5
5
19)
MOV WDTRST, #05Ah
MOV WDTRST, #0A5h
WDIDLE
4
4
(1)
DISRTO
3
3
(1)
SWRST
2
2
Reset Value = 0000 0XX0B
WDTOVF
1
1
(Write-Only)
WDTEN
3709B–MICRO–12/10
0
0

Related parts for AT89LP52-20PU