ATMEGA48PA-MNR Atmel, ATMEGA48PA-MNR Datasheet - Page 319
ATMEGA48PA-MNR
Manufacturer Part Number
ATMEGA48PA-MNR
Description
MCU AVR 4KB FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA48PA-AN.pdf
(448 pages)
Specifications of ATMEGA48PA-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA48A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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28.6
8161D–AVR–10/09
SPI Timing Characteristics
See
Table 28-5.
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 28-3
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
1. In SPI Programming mode the minimum SCK high/low period is:
2. All DC Characteristics contained in this datasheet are based on simulation and characteriza-
- 2 t
- 3 t
tion of other AVR microcontrollers manufactured in the same process technology. These
values are preliminary values representing design targets, and will be updated after character-
ization of actual silicon.
SPI Timing Parameters
CLCL
CLCL
and
for f
for f
(1)
Figure 28-4
CK
CK
< 12 MHz
> 12 MHz
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
for details.
ATmega48PA/88PA/168PA/328P
Min
4 • t
2 • t
10
t
20
20
ck
ck
ck
Typ
See
50% duty cycle
3.6
10
10
0.5 • t
10
10
15
15
10
Table 18-5
sck
Max
1600
319
ns
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