ATMEGA48PA-MNR Atmel, ATMEGA48PA-MNR Datasheet - Page 8
ATMEGA48PA-MNR
Manufacturer Part Number
ATMEGA48PA-MNR
Description
MCU AVR 4KB FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA48PA-AN.pdf
(448 pages)
Specifications of ATMEGA48PA-MNR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, UART, I2C
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
ATMEGA48A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6. AVR CPU Core
6.1
8161D–AVR–10/09
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 6-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
Control Lines
Instruction
Instruction
Program
Memory
Block Diagram of the AVR Architecture
Register
Decoder
Flash
Program
Counter
ATmega48PA/88PA/168PA/328P
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
I/O Module 2
Comparator
I/O Module1
I/O Module n
Watchdog
Interrupt
Timer
Analog
Unit
Unit
SPI
8
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