ATMEGA325A-AUR Atmel, ATMEGA325A-AUR Datasheet - Page 98

• Manufacturer Part Number: ATMEGA325A-AUR
• Description: IC MCU AVR 32K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA325A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6
14.6.1
98
Compare Match Output Unit
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/645
Compare Output Mode and Waveform Generation
The setup of the OC0A should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-
pare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare value.
Changing the COM0A1:0 bits will take effect immediately.
The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator
uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare
match. Also, the COM0A1:0 bits control the OC0A pin output source.
plified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits,
and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-
ters (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the
OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a System
Reset occur, the OC0A Register is reset to “0”.
Figure 14-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform
Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis-
ible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on
the OC0A Register is to be performed on the next compare match. For compare output actions
in the non-PWM modes refer to
4 on page
See ”Register Description” on page 105.
106, and for phase correct PWM refer to
COMnx1
COMnx0
FOCn
clk
I/O
Waveform
Generator
Table 14-3 on page
D
D
D
PORT
DDR
OCnx
Q
Q
Q
Table 14-5 on page
106. For fast PWM mode, refer to
1
0
Figure 14-4
106.
OCn
Pin
8285B–AVR–03/11
shows a sim-
Table 14-