ATMEGA165PV-8ANR Atmel, ATMEGA165PV-8ANR Datasheet - Page 242

• Manufacturer Part Number: ATMEGA165PV-8ANR
• Description: IC MCU AVR 16K 8MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA165PV-8ANR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.6
8019K–AVR–11/10
ATmega165P Boundary-scan Order
Table 23-4.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Table 23-5
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In
PXn. Control corresponds to FF1, and PXn. Pull-up_enable corresponds to FF2. Bit 4, bit 5, bit
6, and bit 7 of Port F is not in the scan chain, since these pins constitute the TAP pins when the
JTAG is enabled.
Table 23-5.
Step
1
2
3
4
5
6
7
8
9
10
11
Bit Number
197
196
195
194
Actions
SAMPLE_P
RELOAD
EXTEST
Verify the
COMP bit
scanned out
to be 0
Verify the
COMP bit
scanned out
to be 1
shows the Scan order between TDI and TDO when the Boundary-scan chain is
Algorithm for Using the ADC
ATmega165P Boundary-scan Order
Signal Name
AC_IDLE
ACO
ACME
AINBG
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Figure 23-3 on page
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
HOLD
1
0
1
1
1
1
0
1
1
1
1
Module
Comparator
233, PXn. Data corresponds to FF0,
PRECH
1
1
1
1
0
1
1
1
1
0
1
PA3.
Data
ATmega165P
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
PA3.
Pull-up_
Enable
0
0
0
0
0
0
0
0
0
0
0
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