ATMEGA165PV-8MNR Atmel, ATMEGA165PV-8MNR Datasheet - Page 83
![IC MCU AVR 16K 8MHZ 64MLF](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA165PV-8MNR
Manufacturer Part Number
ATMEGA165PV-8MNR
Description
IC MCU AVR 16K 8MHZ 64MLF
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165PV-8MNR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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13.2.2
13.3
13.4
8019K–AVR–11/10
Timer/Counter Clock Sources
Counter Unit
Definitions
The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC0A).
Compare Unit” on page 84.
(OCF0A) which can be used to generate an Output Compare interrupt request.
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare unit number, in this case unit A. However, when using the register or bit defines in a
program, the precise form must be used, that is, TCNT0 for accessing Timer/Counter0 counter
value and so on.
The definitions in
Table 13-1.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
13-2
Figure 13-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surroundings.
DATA BUS
“Timer/Counter0 and Timer/Counter1 Prescalers” on page
TCNTn
Timer/Counter Definitions
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is dependent
on the mode of operation.
Table 13-1
for details. The compare match event will also set the Compare Flag
are also used extensively throughout the document.
direction
count
clear
bottom
Control Logic
top
TOVn
(Int.Req.)
clk
Tn
Clock Select
126.
( From Prescaler )
Detector
ATmega165P
Edge
See “Output
Figure
Tn
83
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