ATMEGA64A-AN Atmel, ATMEGA64A-AN Datasheet - Page 124
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA64A-AN
Manufacturer Part Number
ATMEGA64A-AN
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-AN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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15.9.3
8160C–AVR–07/09
Fast PWM Mode
The timing diagram for the CTC mode is shown in
increases until a Compare Match occurs with either OCRnA or ICRn, and then counter (TCNTn)
is cleared.
Figure 15-6. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the
counter will miss the Compare Match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical
level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre-
quency of f
defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared
on the Compare Match between TCNTn and OCRnx, and set at BOTTOM. In inverting Compare
TCNTn
OCnA
(Toggle)
Period
OC
n
A
= f
clk_I/O
1
/2 when OCRnA is set to zero (0x0000). The waveform frequency is
f
OCnA
2
=
-------------------------------------------------- -
2 N
⋅
⋅
(
f
3
1
clk_I/O
+
Figure
OCRnA
4
15-6. The counter value (TCNTn)
)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
ATmega64A
(COMnA1:0 = 1)
124
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