ATMEGA64A-AN Atmel, ATMEGA64A-AN Datasheet - Page 33
![IC MCU AVR 64K FLASH 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA64A-AN
Manufacturer Part Number
ATMEGA64A-AN
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-AN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
- Current page: 33 of 392
- Download datasheet (8Mb)
7.6.5
7.6.6
8160C–AVR–07/09
EEDR – EEPROM Data Register
EECR – EEPROM Control Register
• Bits 15:11 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bits 10:0 – EEAR10:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 2K
bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 2,048.
The Initial Value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
• Bits 7:0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega64A and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is written to one, writing EEWE to one within four clock cycles will write data to
the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no
effect. When EEMWE has been written to one by software, hardware clears the bit to zero after
four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM.
The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM
write takes place. The following procedure should be followed when writing the EEPROM (the
order of steps 3 and 4 is not essential):
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
MSB
R/W
R
7
0
7
–
0
R/W
R
6
–
0
6
0
R/W
R
5
–
0
5
0
R/W
R
4
–
0
4
0
EERIE
R/W
R/W
3
0
3
0
EEMWE
R/W
R/W
2
0
2
0
EEWE
R/W
R/W
1
0
1
X
ATmega64A
EERE
LSB
R/W
R/W
0
0
0
0
EEDR
EECR
33
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