ATMEGA64A-ANR Atmel, ATMEGA64A-ANR Datasheet - Page 37
ATMEGA64A-ANR
Manufacturer Part Number
ATMEGA64A-ANR
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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8. System Clock and Clock Options
8.1
8.1.1
8.1.2
8160C–AVR–07/09
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
I/O
Figure 8-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 8-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clk
CPU
Asynchronous
Timer/Counter
Timer/Counter
Oscillator
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
I/O
is halted, enabling TWI address reception in all sleep modes.
External RC
General I/O
Oscillator
Modules
clk
clk
ASY
I/O
46. The clock systems are detailed below.
External Clock
Control Unit
AVR Clock
Multiplexer
Clock
ADC
clk
Source Clock
ADC
Reset Logic
CPU Core
clk
Oscillator
clk
Crystal
CPU
FLASH
Watchdog Clock
Watchdog Timer
Crystal Oscillator
Low-frequency
Watchdog
Oscillator
RAM
ATmega64A
Calibrated RC
“Power Manage-
Flash and
EEPROM
Oscillator
37
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