ATMEGA128A-MN Atmel, ATMEGA128A-MN Datasheet - Page 174
![IC MCU AVR 128K FLASH 64VQFN](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA128A-MN
Manufacturer Part Number
ATMEGA128A-MN
Description
IC MCU AVR 128K FLASH 64VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 174 of 386
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20. USART
20.1
20.1.1
20.2
8151H–AVR–02/11
Features
Overview
Dual USART
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The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The ATmega128A has two USART’s, USART0 and
USART1. The functionality for both USART’s is described below. USART0 and USART1 have
different I/O registers as shown in
compatibility mode, USART1 is not available, neither is the UBRR0H or UCRS0C Registers.
This means that in ATmega103 compatibility mode, the ATmega128A supports asynchronous
operation of USART0 only.
A simplified block diagram of the USART transmitter is shown in
I/O registers and I/O pins are shown in bold.
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
“Register Summary” on page
367. Note that in ATmega103
Figure
ATmega128A
20-1. CPU accessible
174
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