ATMEGA64L-8AUR Atmel, ATMEGA64L-8AUR Datasheet - Page 191
ATMEGA64L-8AUR
Manufacturer Part Number
ATMEGA64L-8AUR
Description
IC MCU AVR 64K 8MHZ 3V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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UCSRnC – USART
Control and Status
Register C
2490Q–AVR–06/10
(1)
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
Note:
• Bit 7 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, this bit must be written to
zero when UCSRC is written.
• Bit 6 – UMSELn: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 77. UMSEL Bit Settings
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.
If a mismatch is detected, the UPEn flag in UCSRnB will be set.
Table 78. UPM Bits Settings
Bit
Read/Write
Initial Value
UPMn1
1. This register is not available in ATmega103 compatibility mode.
UMSELn
0
0
1
1
0
1
R/W
7
–
0
UMSELn
R/W
6
0
UPMn0
Mode
Asynchronous Operation
Synchronous Operation
UPMn1
0
1
0
1
R/W
5
0
UPMn0
R/W
4
0
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
USBSn
R/W
3
0
UCSZn1
R/W
2
1
UCSZn0
R/W
1
1
ATmega64(L)
UCPOLn
R/W
0
0
UCSRnC
191
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