AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 200

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.3
Table 23-1.
Note:
23.4
23.4.1
23.4.1.1
Table 23-2.
Table 23-3.
200
Name
SDCK
SDCKE
SDCS
BA[1:0]
RAS
CAS
SDWE
NBS[3:0]
A[12:0]
D[31:0]
2
7
2
7
Bk[1:0]
2
6
2
6
I/O Lines Description
1. SDCK is tied low after reset.
Application Example
SAM7SE512/256/32 Preliminary
Bk[1:0]
Bk[1:0]
2
5
2
5
Software Interface
32-bit Memory Data Bus Width
I/O Line Description
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
Bk[1:0]
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
Bk[1:0]
2
4
2
4
Description
SDRAM Clock
SDRAM Clock Enable
SDRAM Controller Chip Select
Bank Select Signals
Row Signal
Column Signal
SDRAM Write Enable
Data Mask Enable Signals
Address Bus
Data Bus
Bk[1:0]
Bk[1:0]
2
3
2
3
Bk[1:0]
2
2
2
2
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
by the user in correlation with the device structure. Various configurations are illustrated.
2
1
2
1
2
0
2
0
Row[11:0]
Table 23-2
1
9
1
9
Row[10:0]
Row[11:0]
1
8
1
8
Row[10:0]
Row[11:0]
1
7
1
7
Row[10:0]
to
Row[11:0]
Table 23-7
1
6
1
6
Row[10:0]
CPU Address Line
CPU Address Line
1
5
1
5
1
4
1
4
illustrate the SDRAM device memory mapping therefore seen
1
3
1
3
1
2
1
2
1
1
1
1
1
0
1
0
9
9
Column[10:0]
Column[10:0]
8
8
Column[9:0]
Column[9:0]
7
Column[8:0]
7
Column[8:0]
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
Column[7:0]
Column[7:0]
6
6
(1)
5
5
4
4
6222F–ATARM–14-Jan-11
3
3
Active Level
High
Low
Low
Low
Low
Low
2
2
1
1
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
0
0