AT91SAM7SE512B-AU Atmel, AT91SAM7SE512B-AU Datasheet - Page 235

• Manufacturer Part Number: AT91SAM7SE512B-AU
• Description: IC ARM7 MCU FLASH 512K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE512B-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Core: ARM7TDMI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26. Peripheral DMA Controller (PDC)
26.1
26.2
6222F–ATARM–14-Jan-11
Overview
Block Diagram
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as
the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral
DMA Controller avoids processor intervention and removes the processor interrupt-handling
overhead. This significantly reduces the number of clock cycles required for a data transfer and,
as a result, improves the performance of the microcontroller and makes it more power efficient.
The PDC channels are implemented in pairs, each pair being dedicated to a particular periph-
eral. One channel in the pair is dedicated to the receiving channel and one to the transmitting
channel of each UART, USART, SSC and SPI.
The user interface of a PDC channel is integrated in the memory space of each peripheral. It
contains:
The peripheral triggers PDC transfers using transmit and receive signals. When the pro-
grammed data is transferred, an end of transfer interrupt is generated by the corresponding
peripheral.
Figure 26-1. Block Diagram
• two 32-bit memory pointer registers (send and receive)
• two 16-bit transfer count register (send and receive)
• two 32-bit register for next memory pointer (send and receive)
• two 16-bit register for next transfer count (send and receive)
Peripheral
Control
THR
RHR
SAM7SE512/256/32 Preliminary
Status & Control
PDC Channel 0
PDC Channel 1
Peripheral DMA Controller
Control
Controller
Memory
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