EFM32G230F64 Energy Micro, EFM32G230F64 Datasheet - Page 178
EFM32G230F64
Manufacturer Part Number
EFM32G230F64
Description
MCU 32BIT 64KB FLASH 64-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32-G230F128-SK.pdf
(65 pages)
2.EFM32-G230F128-SK.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G230F64
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
EFM32G230
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
56
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- EFM32-G230F128-SK PDF datasheet
- EFM32-G230F128-SK PDF datasheet #2
- EFM32G200F16 PDF datasheet #3
- EFM32G200F16 PDF datasheet #4
- Current page: 178 of 463
- Download datasheet (8Mb)
16.3.2.1.1 Parity bit Calculation and Handling
2010-09-06 - d0001_Rev1.00
Table 16.3. USART Data Bits
Table 16.4. USART Stop Bits
The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL.
When MSBF is cleared, data in a frame is sent and received with the least significant bit first. When it
is set, the most significant bit comes first.
The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the
format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL. These bits affect
the entire frame, not only the data bits. An inverted frame has a low idle state, a high start-bit, inverted
data and parity bits, and low stop-bits.
When parity bits are enabled, hardware automatically calculates and inserts any parity bits into outgoing
frames, and verifies the received parity bits in incoming frames. This is true for both asynchronous and
synchronous modes, even though it is mostly used in asynchronous communication. The possible parity
modes are defined in Table 16.5 (p. 179) . When even parity is chosen, a parity bit is inserted to make
the number of high bits (data + parity) even. If odd parity is chosen, the parity bit makes the total number
of high bits odd.
DATA BITS [3:0]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
STOP BITS [1:0]
00
01
10
11
...the world's most energy friendly microcontrollers
178
Number of Data bits
4
5
6
7
8 (Default)
9
10
11
12
13
14
15
16
Number of Stop bits
0.5
1 (Default)
1.5
2
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