EFM32G890F64 Energy Micro, EFM32G890F64 Datasheet - Page 60

• Manufacturer Part Number: EFM32G890F64
• Description: MCU 32BIT 64KB FLASH 112-BGA
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G890F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LFBGA
• Processor Series: EFM32G890
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8.7 Register Description
8.7.1 DMA_STATUS - DMA Status Registers
8.7.2 DMA_CONFIG - DMA Configuration Register
31:21
20:16
15:8
7:4
3:1
0
31:6
5
Offset
0x000
Reset
Access
Name
Bit
Offset
0x004
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
CHNUM
Number of available DMA channels minus one. Always reads as 7, as there are 8 channels.
Reserved
STATE
State can be one of the following. Higher values (11-15) are undefined.
Reserved
EN
When this bit is 1, the DMA is enabled.
Reserved
CHPROT
Name
Name
Value
0
1
2
3
4
5
6
7
8
9
10
Mode
IDLE
RDCHCTRLDATA
RDSRCENDPTR
RDDSTENDPTR
RDSRCDATA
WRDSTDATA
WAITREQCLR
WRCHCTRLDATA
STALLED
DONE
PERSCATTRANS
0x07
0x0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
W
Access
Access
Description
Idle
Reading channel controller data
Reading source data end pointer
Reading destination data end pointer
Reading source data
Writing destination data
Waiting for DMA request to clear
Writing channel controller data
Stalled
Done
Peripheral scatter-gather transition
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Bit Position
Bit Position
60
Channel Number
Control Current State
DMA Enable Status
Channel Protection Control
Description
Description
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