S9S08DZ16F1MLC Freescale Semiconductor, S9S08DZ16F1MLC Datasheet - Page 162

• Manufacturer Part Number: S9S08DZ16F1MLC
• Description: IC MCU 8BIT 16KB FLASH 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ16F1MLC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
162
3. Then, BLPE mode transitions into PBE mode:
4. Last, PBE mode transitions into PEE mode:
c) MCGC1 = 0x98 (%10011000)
d) MCGC3 = 0x44 (%01000100)
e) Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the PLLS
a) Clear LP (bit 3) in MCGC2 to 0 here to switch to PBE mode
b) Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
a) MCGC1 = 0x18 (%00011000)
b) Loop until CLKST (bits 3 and 2) in MCGSC are %11, indicating that the PLL output is selected
– RDIV (bits 5-3) set to %011, or divide-by-8 because 8 MHz / 8= 1 MHz which is in the 1
– PLLS (bit 6) set to 1, selects the PLL. In BLPE mode, changing this bit only prepares the
– VDIV (bits 3-0) set to %0100, or multiply-by-16 because 1 MHz reference * 16 = 16 MHz.
clock is the PLL
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
to feed MCGOUT in the current clock mode
– Now, With an RDIV of divide-by-8, a BDIV of divide-by-1, and a VDIV of multiply-by-16,
MHz to 2 MHz range required by the PLL. In BLPE mode, the configuration of the RDIV
does not matter because both the FLL and PLL are disabled. Changing them only sets up the
the dividers for PLL usage in PBE mode
MCG for PLL usage in PBE mode
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
system clock source
MCGOUT = [(8 MHz / 8) * 16] / 1 = 16 MHz, and the bus frequency is MCGOUT / 2, or 8
MHz
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor