PK10X256VMD100 Freescale Semiconductor, PK10X256VMD100 Datasheet - Page 19

• Manufacturer Part Number: PK10X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK10X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART
• Peripherals: DMA, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 37x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 104
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.2.1 Device clock specifications
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I
Freescale Semiconductor, Inc.
FB_CLK
FB_CLK
Symbol
Symbol
f
f
f
f
LPTMR
LPTMR
FLASH
FLASH
f
f
f
f
SYS
BUS
SYS
BUS
System and core clock
Bus clock
FlexBus clock
Flash clock
LPTMR clock
System and core clock
Bus clock
FlexBus clock
Flash clock
LPTMR clock
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Description
Description
2
C signals.
K10 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 10. General switching specifications
Table 9. Device clock specifications
Table continues on the next page...
Normal run mode
Preliminary
VLPR mode
Min.
Min.
100
100
1.5
16
—
—
—
—
—
—
—
—
—
—
2
Max.
Max.
100
50
50
25
25
25
—
—
—
—
—
2
2
2
1
Bus clock
Bus clock
cycles
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
Notes
Notes
General
1
2
2
2
19