MCIMX283DVM4B Freescale Semiconductor, MCIMX283DVM4B Datasheet - Page 34
MCIMX283DVM4B
Manufacturer Part Number
MCIMX283DVM4B
Description
IC MPU I.MX28 1.2 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX283DVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCIMX283DVM4B
Manufacturer:
TI
Quantity:
332
Part Number:
MCIMX283DVM4B
Manufacturer:
FRESSCALE
Quantity:
20 000
3.4.4.1
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
3.4.4.1.1
The receiver functions correctly up to an ENET0_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET0_RX_CLK frequency.
Figure 9
the figure.
1
3.4.4.1.2
The transmitter functions correctly up to an ENET0_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET0_TX_CLK frequency.
34
M1
M2
M3
M4
ENET0_RX_DV, ENET0_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
ENET0_RXD[3:0] (inputs)
ID
ENET0_RX_CLK (input)
shows MII receive signal timings.
ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER to
ENET0_RX_CLK setup
ENET0_RX_CLK to ENET0_RXD[3:0], ENET0_RX_DV,
ENET0_RX_ER hold
ENET0_RX_CLK pulse width high
ENET0_RX_CLK pulse width low
ENET0_RX_DV
ENET0_RX_ER
ENET MII Mode Timing
MII Receive Signal Timing (ENET0_RXD[3:0], ENET0_RX_DV, ENET0_RX_ER,
and ENET0_RX_CLK)
MII Transmit Signal Timing (ENET0_TXD[3:0], ENET0_TX_EN,
ENET0_TX_ER, and ENET0_TX_CLK)
i.MX28 Applications Processor Data Sheet for Consumer Products, Rev. 0
Figure 9. MII Receive Signal Timing Diagram
Characteristic
Table 38. MII Receive Signal Timing
M1
Table 38
1
M2
describes the timing parameters (M1–M4) shown in
M3
Min.
35%
35%
5
5
M4
Max.
65%
65%
—
—
Freescale Semiconductor
ENET0_RX_CLK
ENET0_RX_CLK
period
period
Unit
ns
ns