PK40X256VMD100 Freescale Semiconductor, PK40X256VMD100 Datasheet - Page 35

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PK40X256VMD100

Manufacturer Part Number
PK40X256VMD100
Description
IC ARM CORTEX MCU 256K 144-MAP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheets

Specifications of PK40X256VMD100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
Peripherals
DMA, I²S, LCD, LVD, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 33x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Rohs Compliant
YES
Processor Series
Kinetis
Core
ARM Cortex M4
Data Ram Size
64 KB
Interface Type
UART, SPI, I2C, I2S, CAN
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
98
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PK40X256VMD100
Manufacturer:
FSL
Quantity:
28
Part Number:
PK40X256VMD100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
where
Freescale Semiconductor, Inc.
• Writes_subsystem — minimum number of writes to each FlexRAM location for
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART;
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
• EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition
• Write_efficiency —
• n
subsystem (each subsystem can have different endurance)
entered with Program Partition command
Partition command
command
nvmcycd
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
— data flash cycling endurance
Figure 9. EEPROM backup writes to FlexRAM
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Peripheral operating requirements and behaviors
35

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