MCIMX253DVM4 Freescale Semiconductor, MCIMX253DVM4 Datasheet - Page 110

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MCIMX253DVM4

Manufacturer Part Number
MCIMX253DVM4
Description
IC MPU I.MX25 COMM 400MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Datasheet

Specifications of MCIMX253DVM4

Core Processor
ARM9
Core Size
32-Bit
Speed
400MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
External Program Memory
Ram Size
144K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.52 V
Data Converters
A/D 3x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 70°C
Package / Case
400-LFBGA
Cpu Speed
400MHz
Embedded Interface Type
EMI, ETHERNET, I2C, SPI, UART, USB
Digital Ic Case Style
BGA
No. Of Pins
400
Supply Voltage Range
1.38V To 1.52V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX253DVM4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
3.7.17.4
Figure 81
(SS22–SS41) used in the figure.
Note:
110
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
• All timings are on pads when SSI is being used for data transfer.
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
SS22
SS23
SS24
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
ID
shows the timing for SSI receiver with external clock.
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
FS (bl) low/high setup before (Tx) CK falling
FS (bl) low/high setup before (Tx) CK falling
FS (wl) low/high setup before (Tx) CK falling
FS (wl) low/high setup before (Tx) CK falling
(Tx/Rx) External FS rise time
(Tx/Rx) External FS fall time
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
AUDn_TXFS (wl)
AUDn_TXFS (bl)
SSI Receiver Timing with External Clock
AUDn_RXD
AUDn_TXC
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
(Input)
(Input)
(Input)
(Input)
Figure 81. SSI Receiver with External Clock Timing Diagram
SS23
Table 84. SSI Receiver Timing with External Clock
Parameter
SS28
SS22
External Clock Operation
SS32
SS35
SS30
SS40
SS26
SS25
Table 84
SS41
–10.0
–10.0
Min.
81.4
36.0
36.0
10.0
10.0
10.0
2.0
describes the timing parameters
SS24
SS34
SS36
Freescale Semiconductor
Max.
15.0
15.0
6.0
6.0
6.0
6.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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