PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 73

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PK40N512VMD100

Manufacturer Part Number
PK40N512VMD100
Description
IC ARM CORTEX MCU 512K 144-MAP
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Datasheets

Specifications of PK40N512VMD100

Core Processor
ARM Cortex-M4
Core Size
32-Bit
Speed
100MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
Peripherals
DMA, I²S, LCD, LVD, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 33x16b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Rohs Compliant
Yes
Processor Series
Kinetis
Core
ARM Cortex M4
Data Ram Size
128 KB
Interface Type
UART, SPI, I2C, I2S, CAN
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
98
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PK40N512VMD100
Manufacturer:
FSL
Quantity:
185
Part Number:
PK40N512VMD100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
9 Revision History
The following table provides a revision history for this document.
Freescale Semiconductor, Inc.
G
A
B
C
D
E
H
F
K
M
J
L
ADC0_DP0/
ADC1_DP0/
ADC0_DP1
ADC1_DP1
ADC1_DP3
ADC0_DP3
PGA0_DP/
PGA1_DP/
USB0_DP
Rev. No.
VOUT33
PTD12
PTD15
PTE10
PTD7
PTE2
PTE6
1
1
1
ADC0_DM0/
ADC1_DM0/
ADC0_DM1
ADC1_DM1
ADC1_DM3
ADC0_DM3
PGA0_DM/
PGA1_DM/
USB0_DM
VREGIN
PTD11
PTD14
PTD6
PTE1
PTE5
PTE9
2
2
ADC0_SE16/
ADC1_SE16/
ADC0_SE21
ADC0_SE22
DAC0_OUT/
ADC0_SE23
VREF_OUT/
ADC1_SE18
CMP1_IN2/
CMP2_IN2/
CMP1_IN3/
CMP1_IN5/
CMP0_IN5/
PTD10
PTD13
PTE12
PTD5
PTE0
PTE4
PTE8
VSS
3
3
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Figure 30. K40 144 MAPBGA Pinout Diagram
11/2010
ADC1_SE23
DAC1_OUT/
Date
CMP2_IN3/
PTE11
PTE28
PTE27
PTE26
PTE24
PTD4
PTD3
PTD2
PTD1
PTE3
PTE7
4
4
Table 46. Revision History
Table continues on the next page...
VREFH
PTC19
PTC18
PTC17
PTE25
VDDA
PTD0
PTA0
VDD
VDD
NC
NC
5
5
Initial public revision
Substantial Changes
EXTAL32
VREFL
PTC16
PTC15
PTC14
PTC13
Preliminary
VSSA
PTA1
PTA2
VBAT
VDD
VSS
6
6
XTAL32
PTC12
PTC11
PTC10
PTC9
PTA6
PTA3
PTA4
VDD
VSS
VSS
VSS
7
7
PTC8
PTC7
PTC6
PTC5
PTA7
PTA8
PTA9
PTA5
VDD
VDD
VSS
VSS
8
8
PTB21
PTB17
PTA13
PTA12
PTA11
PTA10
PTC4
PTB9
PTB5
PTB1
VLL1
VLL2
9
9
VCAP1
VCAP2
PTB20
PTB16
PTA27
PTA16
PTA14
PTB8
PTB4
PTB0
VLL3
VSS
10
10
PTB23
PTB19
PTB11
PTA29
PTA26
PTA17
PTA15
PTA19
PTC3
PTC1
PTB7
PTB3
11
11
Revision History
RESET_b
PTB22
PTB18
PTB10
PTA28
PTA25
PTA24
PTA18
PTC2
PTC0
PTB6
PTB2
12
12
A
B
C
D
G
E
H
F
K
M
J
L
73

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