MCIMX515CJM6CR2 Freescale Semiconductor, MCIMX515CJM6CR2 Datasheet - Page 132

• Manufacturer Part Number: MCIMX515CJM6CR2
• Description: IC MPU I.MX51 529MABGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515CJM6CR2

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Electrical Characteristics
132
SS10
SS12
SS14
SS15
SS16
SS17
SS18
SS19
SS42
SS43
SS52
SS1
SS2
SS3
SS4
SS5
SS6
SS8
ID
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Tx) CK high to FS (bl) high
(Tx) CK high to FS (bl) low
(Tx) CK high to FS (wl) high
(Tx) CK high to FS (wl) low
(Tx/Rx) Internal FS rise time
(Tx/Rx) Internal FS fall time
(Tx) CK high to STXD valid from high impedance
(Tx) CK high to STXD high/low
(Tx) CK high to STXD high impedance
STXD rise/fall time
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
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i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
”Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
Table 102. SSI Transmitter Timing with Internal Clock
Parameter
Synchronous Internal Clock Operation
Internal Clock Operation
NOTE
81.4
36.0
36.0
Min
0.0
30
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Max
15.0
15.0
15.0
15.0
15.0
15.0
15.0
25.0
6.0
6.0
6.0
6.0
6.0
—
—
—
—
—
Unit
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns