KSZ8841-16MBLI Micrel Inc, KSZ8841-16MBLI Datasheet - Page 17

• Manufacturer Part Number: KSZ8841-16MBLI
• Description: IC MAC CTRLR 8/16BIT 128LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8841-16MBLI

• Controller Type: Ethernet Controller, MAC
• Interface: Bus
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

Ball Description for KSZ8841-16 Chip (8/16-Bit)
October 2007
Micrel, Inc.
Ball Number
D10
C10
A10
B10
E8
D9
A8
D8
B8
C8
A7
RDYRTNN
Ball Name
SCAN_EN
TEST_EN
P1LED2
P1LED1
P1LED0
SRDYN
LDEVN
INTRN
PMEN
BCLK
Type
Opu
Opu
Opu
Opu
Opu
Opd
Opd
Ipd
Ipd
I
I
Ball Function
Test Enable
For normal operation, pull-down this ball to ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this ball to ground.
Port 1 LED indicators
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is ball A4.
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous read
cycles. If the host doesn’t connect to this ball, assert this ball.
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
This ball should be tied Low or unconnected if it is in asynchronous mode.
Power Management Event Not
When asserted (Low), this signal indicates that a power management event has
occurred in the system when a wake-up signal is detected by KSZ8841M.
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this ball
need an external 4.7K pull-up resistor.
Local Device Not
P1LED3
P1LED2
P1LED1
P1LED0
P1LED3
P1LED2
P1LED1
P1LED0
2
2
1
defined as follows:
17
Switch Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
—
Link/Act
Full duplex/Col
Speed
Reg. SGCR5 bit [15,9]
[1,0]
Act
Link
Full duplex/Col
Speed
[0,1]
—
100Link/Act
10Link/Act
Full duplex
[1,1]
—
—
—
—
KSZ8841-16/32 MQL/MVL/MBL
M9999-102207-1.6