WJLXT972MLC.A4-864115 Cortina Systems Inc, WJLXT972MLC.A4-864115 Datasheet - Page 30

• Manufacturer Part Number: WJLXT972MLC.A4-864115
• Description: TXRX ETH 10/100 SGL PORT 48-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972MLC.A4-864115

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1044

LXT972M PHY
Datasheet
302875, Revision 5.2
13 September 2007
5.5.1.3
5.5.2
5.6
Cortina Systems
for software. This register bit is cleared when a new negotiation occurs, preventing the
user from reading an old value in Register 6 and assuming there is valid information in
Registers 5 and 8.
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, Cortina recommends the following steps:
Parallel Detection
In parallel with auto-negotiation, the LXT972M PHY also monitors for 10 Mbps Normal
Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device
automatically reverts to the corresponding speed in half-duplex mode. Parallel detection
allows the LXT972M PHY to communicate with devices that do not support auto-
negotiation.
When parallel detection resolves a link, the link must be established in half-duplex mode.
According to IEEE standards, the forced link partner cannot be configured to full-duplex. If
the auto-negotiation link partner does not advertise half-duplex capability at the speed of
the forced link partner, link is not established. The IEEE Standard prevents full-duplex-to-
half-duplex link connections.
MII Operation
This section includes the following topics:
The LXT972M PHY implements the Media Independent Interface (MII) as defined by the
IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC
to the LXT972M PHY (TXD), and for passing data received from the line (RXD) to the
MAC. Each channel has its own clock, data bus, and control signals.
The following signals are used to pass received data to the MAC:
®
1. After power-up, power-down, or reset, the power-down recovery time (specified in
2. Set the Auto-Negotiation Advertisement register bits.
3. Enable auto-negotiation. (Set MDIO register bit 0.12 = 1.)
4. To ensure proper operation, enable or restart auto-negotiation as soon as possible
•
•
•
•
•
•
•
• COL
• CRS
• RX_CLK
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Table 38, RESET_L Pulse Width and Recovery Timing, on page
exhausted before proceeding.
after writing to Register 4.
Section 5.6.1, MII Clocks
Section 5.6.2, Transmit Enable
Section 5.6.3, Receive Data Valid
Section 5.6.4, Carrier Sense
Section 5.6.5, Error Signals
Section 5.6.6, Collision
Section 5.6.7, Loopback
63) must be
5.6 MII Operation
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