WJLXT972MLC.A4-864115 Cortina Systems Inc, WJLXT972MLC.A4-864115 Datasheet - Page 62

• Manufacturer Part Number: WJLXT972MLC.A4-864115
• Description: TXRX ETH 10/100 SGL PORT 48-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972MLC.A4-864115

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1044

LXT972M PHY
Datasheet
302875, Revision 5.2
13 September 2007
Figure 32
Table 37
Figure 33
Cortina Systems
Power-Up Timing
Power-Up Timing
RESET_L Pulse Width and Recovery Timing
®
Voltage threshold
Power Up delay
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance.
LXT972M Single-Port 10/100 Mbps PHY Transceiver
testing.
The PHY comes out of reset after a delay of no more than 300 μ s. System designers should consider this
value as a minimum value. After threshold v1 is reached, the MAC should delay no less than 300 μ s before
accessing the MDIO port.
Parameter
MDIO, and
MDIO, and
RESET_L
2
so on
so on
VCC
Symbol
v1
t1
Min
–
–
v1
Typ
2.9
–
1
Max
300
–
t1
t1
Units
7.2 AC Timing Diagrams and
μ s
B3494-01
V
t2
B3495-01
Test Conditions
–
–
Parameters
Page 62