DS92LV0412SQE/NOPB National Semiconductor, DS92LV0412SQE/NOPB Datasheet - Page 3

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DS92LV0412SQE/NOPB

Manufacturer Part Number
DS92LV0412SQE/NOPB
Description
IC SER/DESER 5-50MHZ 24B 48-LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92LV0412SQE/NOPB

Serdes Function
Deserializer
Data Rate
1.2Gbps
Ic Output Type
CML
No. Of Inputs
2
No. Of Outputs
4
Supply Voltage Range
1.71V To 1.89V, 3V To 3.6V
Driver Case Style
LLP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS92LV0412SQE/NOPBTR
Pin Name
Channel Link Parallel Input Interface
RxIN[3:0]+
RxIN[3:0]-
RxCLKIN+
RxCLKIN-
Control and Configuration
PDB
DS92LV0411 Pin Diagram
DS92LV0411 Pin Descriptions
1, 34, 32, 30,
2, 33, 31, 29
Pin #
28
35
34
23
w/ pull-down
I, LVCMOS
I/O, Type
I, LVDS
I, LVDS
I, LVDS
I, LVDS
Description
True LVDS Data Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
Inverting LVDS Data Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
True LVDS Clock Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
Inverting LVDS Clock Input
These inputs require an external 100 Ω differential termination for standard LVDS levels.
Power-down Mode Input
PDB = 1, Device is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic
high, the PLL is shutdown, IDD is minimized. Control Registers are RESET.
DS92LV0411 — Top View
3
30125219
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