DS92LV0412SQE/NOPB National Semiconductor, DS92LV0412SQE/NOPB Datasheet - Page 4

• Manufacturer Part Number: DS92LV0412SQE/NOPB
• Description: IC SER/DESER 5-50MHZ 24B 48-LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV0412SQE/NOPB

• Serdes Function: Deserializer
• Data Rate: 1.2Gbps
• Ic Output Type: CML
• No. Of Inputs: 2
• No. Of Outputs: 4
• Supply Voltage Range: 1.71V To 1.89V, 3V To 3.6V
• Driver Case Style: LLP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV0412SQE/NOPBTR

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Pin Name
VODSEL
De-Emph
MAPSEL
CONFIG
[1:0]
ID[x]
SCL
SDA
BISTEN
RES[7:0]
Channel Link II Serial Interface
DOUT+
DOUT-
Power and Ground (see NOTE below)
VDDL
VDDP
VDDHS
VDDTX
VDDRX
VDDIO
GND
NOTE: 1= HIGH, 0 L= LOW
The VDD (V
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
25, 3, 36, 27,
18, 13, 12, 8
DDn
Pin #
10, 9
DAP
and V
20
19
26
21
16
15
11
14
17
24
22
4
6
7
5
DDIO
) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
I/O, LVCMOS
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
w/ pull-down
I, LVCMOS
I, LVCMOS
I, LVCMOS
I, LVCMOS
Open Drain
I, LVCMOS
I, LVCMOS
I/O, Type
w/ pull-up
I, Analog
I, Analog
O, CML
O, CML
Ground
Power
Power
Power
Power
Power
Power
Description
Differential Driver Output Voltage Select — Pin or Register Control
VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)
De-Emphasis Control — Pin or Register Control
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See
Channel Link Map Select — Pin or Register Control
MAPSEL = 1, MSB on RxIN3+/-.
MAPSEL = 0, LSB on RxIN3+/-.
Operating Modes
Determines the device operating mode and interfacing device.
CONFIG[1:0] = 00: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to 3.3V
Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor to 3.3V
BIST Mode — Optional
BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
Reserved - tie LOW
True Output.
The output must be AC Coupled with a 0.1 μF capacitor.
Inverting Output.
The output must be AC Coupled with a 0.1 μF capacitor.
Logic Power, 1.8 V ±5%
PLL Power, 1.8 V ±5%
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
RX Power, 1.8 V ±5%
LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10%
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
Table 4
4
Figure 20
Figure 21
Table
10.
Table 1