DS92LV2421SQE/NOPB National Semiconductor, DS92LV2421SQE/NOPB Datasheet - Page 24

• Manufacturer Part Number: DS92LV2421SQE/NOPB
• Description: IC SER/DESER 10-75MHZ 24B 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2421SQE/NOPB

• Serdes Function: Serialiser
• Ic Input Type: LVCMOS
• Ic Output Type: CML
• No. Of Inputs: 1
• No. Of Outputs: 1
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 48
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LV2421SQE/NOPBTR

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1.8V or 3.3V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate
with 1.8 V or 3.3 V levels (V
ibility. The 1.8 V levels will offer a lower noise (EMI) and also
a system power savings.
Power Saving Features
Des — PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN
the device. This pin can be controlled by the system to save
power, disabling the Des when the display is not needed. An
SSC3
SSC3
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
LF_MODE = L (20 - 65 MHz)
LH_MODE = H (10 - 20 MHz)
SSC2
SSC2
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
DDIO
SSC[3:0] Inputs
SSC[3:0] Inputs
TABLE 7. SSCG Configuration (LF_MODE = H) — Des Output
TABLE 6. SSCG Configuration (LF_MODE = L) — Des Output
) for target (Display) compat-
SSC1
SSC1
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
SSC0
SSC0
H
H
H
H
H
H
H
H
24
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
auto detect mode is also available. In this mode, the PDB pin
is tied High and the Des will enter POWER DOWN when the
serial stream stops. When the serial stream starts up again,
the Des will lock to the input stream and assert the LOCK pin
and output valid data. In POWER DOWN mode, the Data and
CLKOUT output states are determined by the OSS_SEL sta-
tus. Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
Des — Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input
serial stream is stopped. A STOP condition is detected when
fdev (%)
fdev (%)
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
NA
NA
Result
Result
fmod (kHz)
fmod (kHz)
CLK/2168
CLK/1300
CLK/868
CLK/650
CLK/620
CLK/370
CLK/258
CLK/192
Disable
Disable