DS92LX2121SQE/NOPB National Semiconductor, DS92LX2121SQE/NOPB Datasheet - Page 11

• Manufacturer Part Number: DS92LX2121SQE/NOPB
• Description: IC SER/DESER 10-50MHZ 40-LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX2121SQE/NOPB

• Serdes Function: Serializer
• Data Rate: 100Kbps
• Ic Output Type: CML
• No. Of Inputs: 21
• No. Of Outputs: 2
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: LLP
• No. Of Pins: 40
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS92LX2121SQE/NOPBTR

t
λ
δ
δ
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
f
JINT
RCP
PDC
CLH
CHL
CLH
CHL
ROS
ROH
DD
DDLT
RJIT
DCJ
DPJ
DCCJ
DEV
MOD
Symbol
STXBW
STX
STXf
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Receiver Output Clock Period
PCLK Duty Cycle
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
Deserializer Delay
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Deserializer Clock Jitter
Deserializer Period Jitter
Deserializer Cycle-to-Cycle Clock
Jitter
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
Peak-to-peak Serializer
Output Jitter
Serializer Jitter Transfer
Function -3 dB Bandwidth
Serializer Jitter Transfer
Function (Peaking
Serializer Jitter Transfer
Function (Peaking
Frequency)
Parameter
Parameter
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
PCLK = 50MHz
PCLK = 50 MHz Default Registers
PCLK = 50 MHz Default Registers
PCLK = 50 MHz Default Registers
t
V
or 3.0 V to 3.6 V,
CL = 8pF (lumped load)
Default Registers
( )
V
or 3.0 V to 3.6 V,
CL = 8pF (lumped load)
Default Registers
(Figure
V
or 3.0 V to 3.6 V, CL =
8pF (lumped load)
Default Registers
Default Registers
Register 0x03h b[0]
(RRFB = 1)
Figure 14
(Note
(Note
PCLK
SSCG[3:0] = OFF
(Note
PCLK
SSCG[3:0] = OFF
(Note
PCLK
SSCG[3:0] = OFF
(Note
LVCMOS Output Bus
SSC[3:0] = ON
Figure 16
RCP
DDIO
DDIO
DDIO
(Note
= t
: 1.71 V to 1.89 V
: 1.71 V to 1.89 V
: 1.71 V to 1.89 V
5)
13,
6,
7,
8,
Conditions
TCP
13)
Note
Note
Note
10)
Note
(Note
Conditions
11)
11)
11)
14)
10)
11
PCLK
PCLK
Deserializer PCLK
Output
Deserializer Data
Outputs
Deserializer Data
Outputs
10 MHz - 50 MHz
10 MHz - 50 MHz
50 MHz
10 MHz
50 MHz
10 MHz
50 MHz
10 MHz
50 MHz
20 MHz - 50 MHz
20 MHz - 50 MHz
Pin/Freq.
Min
4.571T +
0.38T
0.38
Min
1.3
1.3
1.6
1.6
20
45
8
0.396
0.944
1.90
Typ
500
4.571T +
±0.5% to
9 kHz to
66 kHz
±2.0%
0.5T
0.53
Typ
300
120
425
320
320
300
2.0
2.0
2.4
2.4
0.5
50
12
T
Max
4.571T
Max
+ 16
100
550
250
600
480
500
500
2.8
2.8
3.3
3.3
55
10
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Units
MHz
kHz
dB
UI
Units
kHz
ms
ns
ns
ns
ns
ps
ps
ps
UI
%
%
T