DS90UR907QSQX/NOPB National Semiconductor, DS90UR907QSQX/NOPB Datasheet
DS90UR907QSQX/NOPB
Specifications of DS90UR907QSQX/NOPB
Related parts for DS90UR907QSQX/NOPB
DS90UR907QSQX/NOPB Summary of contents
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... EMI data transfer. The device is offered in a 36-pin LLP package and is specified over the automotive AEC-Q100 Grade 2 temperature range of -40˚C to +105˚C. Applications Diagram TRI-STATE® registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation DS90UR907Q Features ■ ...
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DS90UR907Q Pin Diagram Pin Descriptions Pin Name Pin # I/O, Type FPD-Link Input Interface RxIN[3:0]+ 2, 33, 31 LVDS RxIN[3:0]- 1, 34, 32, 30, I, LVDS 28 RxCLKIN LVDS RxCLKIN LVDS www.national.com DS90UR907Q — ...
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Pin Name Pin # I/O, Type Control and Configuration PDB 23 I, LVCMOS w/ pull-down VODSEL 20 I, LVCMOS w/ pull-down De-Emph 19 I, Analog w/ pull-up MAPSEL 26 I, LVCMOS w/ pull-down CONFIG 10 LVCMOS [1:0] w/ ...
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Block Diagrams Ordering Information NSID Package Description DS90UR907QSQE 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS90UR907QSQ 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS90UR907QSQX 36–pin LLP, 6.0 X 6.0 X 0.8 mm, ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS I/O Voltage −0. LVDS Input Voltage −0. Driver Output Voltage Junction Temperature ...
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Symbol Parameter FPD-LINK II LVDS DRIVER DC SPECIFICATIONS V Differential Output Voltage OD Differential Output Voltage V ODp-p (DOUT+) – (DOUT-) ΔV Output Voltage Unbalance OD Offset Voltage – Single-ended & B, Figure 2 Offset ...
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Symbol Parameter FPD-LINK II LVDS OUTPUT t Output Low-to-High Transition HLT Time Figure 4 t Output High-to-Low Transition HLT Time Figure 4 t Ouput Active to OFF Delay, XZD Figure 7 t PLL Lock Time, Figure 6 PLD t Delay ...
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DC and AC Serial Control Bus Characteristics Over 3.3V supply and temperature ranges unless otherwise specified. Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis SDA RiseTime ...
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AC Timing Diagrams and Test Circuits FIGURE 1. FPD-Link DC VTH/VTL Definition FIGURE 2. Output Test Circuit FIGURE 3. Output Waveforms FIGURE 4. Output Transition Times 9 30105062 30105046 30105030 30105047 www.national.com ...
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FIGURE 5. FPD-Link Input Jitter Tolerance 10 30105061 ...
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FIGURE 6. Lock Time FIGURE 7. Disable Time FIGURE 8. Latency Delay 11 30105048 30105049 30105010 www.national.com ...
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FIGURE 9. Output Jitter FIGURE 10. Checkerboard Data Pattern FIGURE 11. BIST PASS Waveform FIGURE 12. Serial Control Bus Timing Diagram 12 30105050 30105032 30105052 30105036 ...
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FIGURE 13. Typical IDDT (1.8V Supply) Current as a function of RxCLK 13 30105001 www.national.com ...
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Functional Description The DS90UR907Q converter transmits an FPD-Link interface (4 LVDS data channels + 1 LVDS clock) with total of 27–bits of data (24–high speed bits and 3 low speed video control signals) over a single serial FPD-Link II pair. ...
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FIGURE 15. Video Control Signal Filter Wavefrom COLOR BIT MAPPING SELECT The DS90UR907Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs on RxIN FIGURE 16. 8–bit FPD-LInk Mapping: LSB's on RxIN3 30105042 [3] ...
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EMI REDUCTION FEATURES Spread Spectrum Compatibility The RxCLKIN of the FPD-Link input is capable of tracking spread spectrum clocking (SSC) from a host source. The Rx- CLKIN will accept spread spectrum, tracking up to 35kHz modulation and ±0.5, ±1 or ...
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Stop Clock Feature The DS90UR907Q will enter a low power SLEEP state when the RxCLKIN is stopped. A STOP condition is detected when the input clock frequency is less than 3 MHz. The clock should be held at a static ...
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FIGURE 19. BIST Mode Flow Diagram Optional Serial Bus Control The DS90UR907Q may be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration ...
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The third pin is the ID[X] pin. This pin sets one of four possible device addresses. Two different connections are possible. The pin may be pulled to V (1.8V, NOT V DD kΩ resistor kΩ pull up ...
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ADD ADD Register Name Bit(s) (dec) (hex Ser Config 1 4 Device ID 6 De-Emphasis 7:5 Control 3:0 www.national.com TABLE 5. Serial Bus Control Registers R/W Defa Function ult (bin) 7 R/W 0 Reserved ...
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Applications Information DISPLAY APPLICATION The DS90UR907Q and DS90UR908Q chipset is intended for interface between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats RGB888 application, ...
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POWER UP REQUIREMENTS AND PDB PIN The VDD (V and V ) supply ramp should be faster than DDn DDIO 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed ...
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PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to ...
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Revision History • 03/30/2010 — Initial Release • 04/14/2010 — Update Table 5 Addr 0[4:2] = Reserved' Addr 0[5] = VODSEL www.national.com • 06/22/2010 — Update all final AC and DC parameter limits; Add typical IDDT curve • 07/26/2010 — ...
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Physical Dimensions inches (millimeters) unless otherwise noted 36–pin LLP Package (6 6 0.8 mm, 0.5 mm pitch) NS Package Number SQA36AC 25 www.national.com ...
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