LS027B7DH01 Sharp Microelectronics, LS027B7DH01 Datasheet - Page 19

LCD Graphic Display Modules & Accessories 2.7 WQVGA HR-TFT 400x240 w/FPC

LS027B7DH01

Manufacturer Part Number
LS027B7DH01
Description
LCD Graphic Display Modules & Accessories 2.7 WQVGA HR-TFT 400x240 w/FPC
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LS027B7DH01

Pixel Density
400 x 240
Module Size (w X H X T)
62.8 mm x 42.82 mm
Viewing Area (w X H)
58.8 mm x 35.28 mm
Operating Temperature Range
- 20 C to + 70 C
Attached Touch Screen
No
Product
2.7 in WQVGA Monochrome
Display Mode
Transmissive
Interface
Serial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
LS027B7DH01
Manufacturer:
SAMSUNG
Quantity:
1 000
Part Number:
LS027B7DH01A
Manufacturer:
SHARP
Quantity:
1 000
6-5-2 Data Update Mode (Multiple Lines)
SCS
SI
SCLK
GL(n-1)th line
Updates arbitrary multiple lines data. (M0=”H”、M2=”L”)
D399
tsSCS
tsSI
D400
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
M1: Frame inversion flag.
M2: All clear flag.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
* For gate line address setting, refer to 6-6) Input Signal and Display.
* Input data continuously.
* M1: Frame inversion flag is enabled when EXTMODE=”L”.
* When SCS becomes “L”, M0 and M2 are cleared.
M0
DUMMY DATA(don't care)
thSI
M1
※ Data write period
※ Data transfer period
M2
(8ck(Dummy)+8ck(address)=16ck)
Gate line address select period
Mode select period
(3ck+5ckDMY)
Data is being stored in 1
DMY
AG0
When “L”, display mode (maintain memory internal data).
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
Refer to 6-5-4) All Clear Mode to execute clear.
DMY
AG1
twSCLKL
For example, during GL2nd line data transfer period, GL 2
line data is transferred from 1
DMY
DMY
AG4
twSCLKH
GL(n)th line
DMY
AG5
AG0
AG6
AG1
AG7
twSCSH
twSCSH
Gate line address select period
AG2
D1
AG3
D2
(8ck)
GL1st line
st
AG4
Date write period
latch block of binary driver on panel.
(400ck)
D398
AG5
D399
AG6
SPEC No.
LCY-1210401A
D400
AG7
st
latch to pixel internal memory circuit at the same time.
D1
D2
D3
Date write period
D4
Date transfer period
(400ck)
DUMMY DATA(don't care)
(16ck)
D397
D398
MODEL No.
D399
LS027B7DH01
D400
DUMMY DATA(don't care)
nd
(8ck(Dummy)+8ck(address)=16ck)
line address is latched and GL1st
AG0
Date transfer period
thSCS
AG1
GL2nd line
AG5
twSCSL
AG6
PAGE
AG7
D1
D2
16

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