DS1843D+ Maxim Integrated Products, DS1843D+ Datasheet - Page 3

• Manufacturer Part Number: DS1843D+
• Description: Sample & Hold Amplifiers IC FAST SAMPLE HOLD CIRCUIT
• Manufacturer: Maxim Integrated Products

Specifications of DS1843D+

• Acquisition Time: 260 ns to 300 ns
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: uDFN-8
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC ELECTRICAL CHARACTERISTICS
(V
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Guaranteed by design.
Note 3: V
Note 4: The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin
Note 5: V
Note 6: Voltage step applied across V
Sample Time Minimum (Note 3)
Delay Time Minimum
Output Time
Hold Time
Output Step Recovery Time
(Note 6)
CC
= +2.97V to +5.5V, T
V
by an ADC while it is sampling the DS1843’s output. See the Output Buffer section. Settled within 1% of initial voltage.
OUTP
series to both V
must be low for a short period of time, t
OUT
OUT
V
EXTERNAL
ADC DATA
t
t
DEN IS CONNECTED TO V
NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS.
ADC:ST
ADC:CT
PARAMETER
INP
- V
- V
OUTN
at the end of the 10μs hold time is within specified % of V
at the end of the hold time is within 1% of V
SEN
INN
= EXTERNAL ADC SAMPLING TIME.
= EXTERNAL ADC CONVERSION TIME.
_______________________________________________________________________________________
INP
A
and V
= -40°C to +85°C, unless otherwise noted.) (See the Timing Diagram .)
CC
FOR DIFFERENTIAL OUTPUT.
INN
(V
SYMBOL
OUTP
INP
t
HOLD
t
t
t
OUT
REC
DEL
t
S
- V
to V
INN
DEL
OUTN
= 1V). External capacitance to ground for both V
V
V
(Note 4)
Delay from SEN falling edge until valid
output at V
(Note 5)
1V step, DEN = high
3V step, DEN = high or low
t
S
OUT
OUT
, before the input changes.
Fast Sample-and-Hold Circuit
through a 5pF capacitor connected to each pin. This models the load presented
VOLTAGE INVALID
is within 1%
is within 35%
IN
t
DEL
during the sample window (V
OUT
CONDITIONS
to 1% accuracy
t
OUT
IN
during the sample window; a 2.5kΩ resistor connected in
t
REC
t
ADC:ST
t
ADC:CT
INP
t
HOLD
- V
INP
INN
t
MIN
300
260
OUT
10
and V
= 1V).
DATA VALID
Timing Diagram
INN
TYP
is approximately 10pF.
MAX
100
3.5
2
2
UNITS
ns
ns
μs
μs
μs
3