DS1843D+ Maxim Integrated Products, DS1843D+ Datasheet - Page 6

• Manufacturer Part Number: DS1843D+
• Description: Sample & Hold Amplifiers IC FAST SAMPLE HOLD CIRCUIT
• Manufacturer: Maxim Integrated Products

Specifications of DS1843D+

• Acquisition Time: 260 ns to 300 ns
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: uDFN-8
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Fast Sample-and-Hold Circuit
The DS1843 consists of a fully differential sampling
capacitor, switches, and a differential output buffer. It is
designed to operate in fiber optic burst-mode systems;
however, it can be used in other applications requiring
a fast sample-and-hold circuit. The output can be con-
figured for single-ended operations.
The input voltage is sampled using a 5pF capacitor on
the positive input and another on the negative input.
The capacitors are connected to the input when SEN is
high. In addition to the sampling capacitors, the inputs
6
GND
V
V
SEN
V
INP
INN
CC
_______________________________________________________________________________________
PIN
1
2
3
4
5
6
7
8
C
C
NAME
IN
IN
V
V
GND
V
V
DEN
SEN
V
OUTN
OUTP
INP
INN
CC
CONTROL
LOGIC
Detailed Description
Input Sampling Capacitor
DS1843
Power-Supply Input
Positive Voltage Input. Input to sample circuit.
Negative Voltage Input. Input to sample circuit.
Differential Output Enable. Connect to V
Ground Terminal
Sampled Voltage Negative Output. Buffered output of the hold capacitor. Keep unconnected or
connect to GND for single-ended output mode.
Sampled Voltage Positive Output and Single-Ended Output. Buffered output of the hold capacitor.
Sample Enable. Enables input sampling. This input is pulsed.
C
C
S
S
Block Diagram
DEN
V
V
OUTN
OUTP
also have parasitic capacitance (C
tors must fully charge before SEN is switched to low in
order to ensure accurate sampling. An RC time con-
stant is created by the resistance of the voltage source
connected to the DS1843’s input and the capacitances
on this node. See the Applications Information section
for details.
After sampling is complete, the sampling capacitor is
switched to the output buffer. This buffer requires a
small amount of time to settle, t
used to measure the DS1843’s output, a step occurs at
the ADC’s input caused by the ADC’s internal sampling
capacitor. The DS1843’s recovery time, t
dent on the size of the ADC’s sampling capacitor and
the voltage applied across the ADC. To maximize
accuracy, the ADC’s sampling speed (ADC clock fre-
quency) should be reduced until the ADC’s conversion
window (t
larger than the DS1843’s recovery time. Refer to the
ADC’s documentation for t
As the sampling time (t
increases. The output error is largely dependent on the
settling time of the sampling capacitor and, to a lesser
degree, the output buffer’s gain error and offset volt-
age. Settling time can be reduced by driving the
DS1843 with a lower impedance. In a typical fiber optic
application, a current is applied across a 5kΩ resistor.
By using a stronger current source, the resistance and
the settling time can be reduced (see the Applications
Information section for details).
CC
for differential output or GND for single-ended output.
FUNCTION
ADC:ST
Sampling Time and Output Error
, as shown in the Timing Diagram ) is
S
) is decreased, the output error
ADC:ST
Pin Description
OUT
.
IN
. When an ADC is
Output Buffer
). These capaci-
REC
, is depen-