ispPAC-CLK5610AV-01TN48I Lattice, ispPAC-CLK5610AV-01TN48I Datasheet - Page 15

• Manufacturer Part Number: ispPAC-CLK5610AV-01TN48I
• Description: Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ispPAC-CLK5610AV-01TN48I

• Max Input Freq: 400 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Timing Diagrams
Figure 1-8. Erase (User Erase or Erase All) Timing Diagram
Figure 1-9. Programming Timing Diagram
Figure 1-10. Verify Timing Diagram
Figure 1-11. Discharge Timing Diagram
State
TCK
TMS
TMS
TCK
State
State
TCK
TMS
State
VIH
VIH
TCK
VIL
VIL
TMS
VIH
VIH
VIL
VIL
Update-IR
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
Update-IR
t
SU1
Update-IR
Update-IR
t
SU1
t
SU1
t
SU1
t
CKH
t
H
t
CKH
t
H
Run-Test/Idle (Erase or Program)
t
SU1
t
CKH
t
t
t
CKL
SU1
CKH
t
t
H
t
GKL
H
Run-Test/Idle (Erase)
t
SU1
t
SU1
t
CKL
t
CKL
t
Run-Test/Idle (Program)
H
t
Run-Test/Idle (Program)
H
t
PWP
t
t
H
t
or t
BEW
H
BEW
t
t
SU1
SU1
t
PWP
t
PWV
Select-DR Scan
t
Select-DR Scan
t
CKH
CKH
t
t
t
SU1
t
H
H
SU1
1-15
t
Select-DR Scan
CKH
Select-DR Scan
t
CKH
t
t
H
H
t
SU1
t
SU1
ispClock5600A Family Data Sheet
t
HVDIS
t
CKH
(Actual)
t
t
CKH
H
t
H
t
Run-Test/Idle (Discharge)
t
t
SU1
SU1
SU1
t
GKL
t
Run-Test/Idle (Verify)
SU1
t
CKL
t
Specified by the Data Sheet
CKH
t
t
t
CKH
H
CKH
t
Update-IR
Specified by the Data Sheet
CKH
Update-IR
t
t
H
H
t
H
t
SU2
t
t
SU1
SU1
t
PWV
t
t
CKL
CKL
t
SU1
t
Actual
SU1
t
PWV
t
t
CKH
CKH
t
t
t
H
H
CKH
t
H
t
CKH
t
H