ispPAC-CLK5610AV-01TN48I Lattice, ispPAC-CLK5610AV-01TN48I Datasheet - Page 45

• Manufacturer Part Number: ispPAC-CLK5610AV-01TN48I
• Description: Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ispPAC-CLK5610AV-01TN48I

• Max Input Freq: 400 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispClock5600A Family Data Sheet
GOE – Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE
also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock.
PS0, PS1 – These input pins are used to select one of four user-defined configuration profiles for the device.
PLL_BYPASS – When this pin is pulled LOW, the V-dividers are driven from the output of the device’s VCO, and
the device behaves as a phase-locked loop. When this pin is pulled HIGH, the V-dividers are driven directly from
the output of the M-divider, and the PLL functions are effectively bypassed.
RESET – When this pin is pulled HIGH, all on-board counters are reset, and lock is lost.
TEST1,TEST2 – These pins are used for factory test functions, and should always be tied to ground.
n/c – These pins have no internal connection. We recommend that they be left unconnected.
RESERVED – These pins are reserved for factory use and should be left unconnected.
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