FM22L16-55-TG Ramtron, FM22L16-55-TG Datasheet - Page 2

• Manufacturer Part Number: FM22L16-55-TG
• Description: F-RAM 4M (256Kx16) 55ns
• Manufacturer: Ramtron

Specifications of FM22L16-55-TG

• Organization: 256 Kbit x 16
• Access Time: 55 ns
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Memory Size: 4 Mbit
• Interface: Parallel
• Package / Case: TSOP-44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
Rev. 2.0
Apr. 2011
Pin Name
A(16:0)
/CE
/WE
/OE
/ZZ
DQ(15:0)
/UB
/LB
VDD
VSS
UB, LB
WE
ZZ
A(16:0)
CE
OE
Supply
Supply
2
Type
Input
Input
Input
Input
Input
Input
Input
I/O
Pin Description
Address inputs: The 17 address lines select one of 131,072 words in the F-RAM array. The
lowest two address lines A(1:0) may be used for page mode read and write operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is low
and /ZZ is high. The entire address is latched internally on the falling edge of /CE. Subsequent
changes to the A(1:0) address inputs allow page mode operation when /CE is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21L16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM21L16 drives the data bus when valid read data is
available. Deasserting /OE high tri-states the DQ pins.
Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for normal
read/write operation. If unused, tie /ZZ to V
Data: 16-bit bi-directional data bus for accessing the F-RAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z if /UB
is high. If the user does not perform byte writes and the device is not configured as a 256Kx8,
the /UB and /LB pins may be tied to ground.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z if /LB
is high. If the user does not perform byte writes and the device is not configured as a 256Kx8,
the /UB and /LB pins may be tied to ground.
Supply Voltage
Ground
Control
Logic
A(1:0)
A(16:2)
Figure 1. Block Diagram
16K x 16 block
16K x 16 block
16K x 16 block
16K x 16 block
DD
I/O Latch & Bus Driver
.
Column Decoder
16K x 16 block
16K x 16 block
16K x 16 block
16K x 16 block
FM21L16 - 128Kx16 FRAM
DQ(15:0)
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