FM25V10-G Ramtron, FM25V10-G Datasheet - Page 6

• Manufacturer Part Number: FM25V10-G
• Description: F-RAM 1M (128Kx8) 2.0-3.6V
• Manufacturer: Ramtron

Specifications of FM25V10-G

• Organization: 128 K x 8
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Memory Size: 1 Mbit
• Interface: SPI
• Package / Case: SOIC-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /W pin must be high or inactive. Prior
Status Register & Write Protection
The write protection features of the FM25V10 are
multi-tiered. Taking the /W pin to a logic low state is
the hardware write-protect function. Status Register
write operations are blocked when /W is low. To
write the memory with /W high, a WREN op-code
must first be issued. Assuming that writes are enabled
using WREN and by /W, writes to memory are
controlled by the Status Register. As described
above, writes to the Status Register are performed
using the WRSR command and subject to the /W pin.
The Status Register is organized as follows.
Table 2. Status Register
Bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and
none of these bits can be modified. Note that bit 0
(“Ready” in Serial Flash) is unnecessary as the F-
RAM writes in real-time and is never busy, so it
reads out as a ‘0’. There is an exception to this when
the device is waking up from Sleep Mode, which is
described on the following page. The BP1 and BP0
control software write protection features. They are
nonvolatile (shaded yellow). The WEL flag indicates
the state of the Write Enable Latch. Attempting to
directly write the WEL bit in the Status Register has
Rev. 2.0
May 2010
Bit
Name
S
C
D
Q
S
C
D
Q
WPEN
7
6
1
5
0
4
0
BP1
3
Figure 8. WRSR Bus Configuration
BP0
Figure 7. RDSR Bus Configuration
2
WEL
1
0
0
to sending the WRSR command, the user must send
a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
no effect on its state. This bit is internally set and
cleared via the WREN and WRDI commands,
respectively.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 3. Block Memory Write Protection
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware /W
pin. When WPEN is low, the /W pin is ignored.
When WPEN is high, the /W pin controls write
access to the Status Register. Thus the Status Register
is write protected if WPEN=1 and /W=0.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
BP1
0
0
1
1
BP0
0
1
0
1
Protected Address Range
None
18000h to 1FFFFh (upper ¼)
10000h to 1FFFFh (upper ½)
00000h to 1FFFFh (all)
FM25V10 - 1Mb SPI FRAM
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