FM25V10-G Ramtron, FM25V10-G Datasheet - Page 7

• Manufacturer Part Number: FM25V10-G
• Description: F-RAM 1M (128Kx8) 2.0-3.6V
• Manufacturer: Ramtron

Specifications of FM25V10-G

• Organization: 128 K x 8
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Memory Size: 1 Mbit
• Interface: SPI
• Package / Case: SOIC-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

under any circumstances. This occurs if the BP1 and
BP0 bits are set to 1, the WPEN bit is set to 1, and
the /W pin is low. This occurs because the block
protect bits prevent writing memory and the /W
signal in hardware prevents altering the block protect
Table 4. Write Protection
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike Serial
Flash, the FM25V10 can perform sequential writes at
bus speed. No page buffer is needed and any number
of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a three-byte address
value, which specifies the 17-bit address of the first
data byte of the write operation. Subsequent bytes are
data and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of
1FFFFh is reached, the counter will roll over to
00000h. Data is written MSB first. A write operation
is shown in Figure 9.
Unlike Serial Flash, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8
op-code operation. Asserting /W active in the middle
of a write operation will have no effect until the next
falling edge of /S.
Read Operation
After the falling edge of /S, the bus master can issue
a READ op-code. Following this instruction is a
three-byte address value (A16-A0), specifying the
address of the first data byte of the read operation.
After the op-code and address are complete, the D
pin is ignored. The bus master issues 8 clocks, with
Rev. 2.0
May 2010
th
clock). The rising edge of /S terminates a WRITE
WEL
0
1
1
1
WPEN
X
0
1
1
/W
X
X
0
1
Protected Blocks
Protected
Protected
Protected
Protected
bits (if WPEN is high). Therefore in this condition,
hardware must be involved in allowing a write
operation. The following table summarizes the write
protection conditions.
one bit read out for each. Addresses are incremented
internally as long as the bus master continues to issue
clocks. If the last address of 1FFFFh is reached, the
counter will roll over to 00000h. Data is read MSB
first. The rising edge of /S terminates a READ op-
code operation and tri-states the Q pin.
operation is shown in Figure 10.
Fast Read Operation
The FM25V10 supports the FAST READ op-code
(0Bh) that is found on Serial Flash devices. It is
implemented for code compatibility with Serial Flash
devices. Following this instruction is a three-byte
address (A16-A0), specifying the address of the first
data byte of the read operation. A dummy byte
follows the address. It inserts one byte of read
latency. The D pin is ignored after the op-code, 3-
byte address, and dummy byte are complete. The bus
master issues 8 clocks, with one bit read out for each.
The Fast Read operation is otherwise the same as an
ordinary READ. If the last address of 1FFFFh is
reached, the counter will roll over to 00000h. Data is
read MSB first. The rising edge of /S terminates a
FAST READ op-code operation and tri-states the Q
pin. A Fast Read operation is shown in Figure 11.
Hold
The FM25V10 and FM25VN10 devices have a
/HOLD pin that can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while C is low, the current
operation will pause. Taking the /HOLD pin high
while C is low will resume an operation. The
transitions of /HOLD must occur while C is low, but
the C and /S pins can toggle during a hold state.
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
FM25V10 - 1Mb SPI FRAM
Status Register
Protected
Unprotected
Protected
Unprotected
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