MAXQ7670ATL+ Maxim Integrated Products, MAXQ7670ATL+ Datasheet - Page 25

• Manufacturer Part Number: MAXQ7670ATL+
• Description: Microcontrollers (MCU) MICROCNTRLR W/10-BIT ADC PGA 64KB FLASH & CAN INTRFCE
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ7670ATL+

• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• Interface Type: SPI, JTAG, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-40
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The SPI clock frequency is limited to SYSCLK/2 in mas-
ter mode and SYSCLK/8 in slave mode. Figure 10
shows the functional diagram of the SPI port. Figures 1
and 2 illustrate the timing parameters listed in the
Electrical Characteristics table.
The MAXQ7670A provides seven general-purpose digi-
tal I/Os (GPIOs). Some of the GPIOs include an addi-
tional special function (SF), such as a timer
input/output. For example, the state of P0.6/T0 is pro-
grammable to depend on timer channel 0 logic. When
used as a port, each I/O is configurable for high-imped-
ance, weak pullup to DVDDIO or pulldown to GNDIO.
Figure 10. SPI Functional Diagram
SPI INTERRUPT
SYSCLK
SFR DATA BUS
MSB (15)
______________________________________________________________________________________
General-Purpose Digital I/Os
/2 MASTER (MAX)
/8 SLAVE (MAX)
PGA, 64KB Flash, and CAN Interface
SPI CONTROL UNIT
SHIFT REGISTER
READ BUFFER
MAXQ7670A
Microcontroller with 12-Bit ADC,
SHIFT CLK
LSB(0)
SCLK OUT
SCLK IN
MASTER/SLAVE SELECT
SPI ENABLE
7
SPI CONTRL REG (SPICN)
SPI CONTRL REG (SPICF)
SPI CONTRL REG (SPICK)
At power-up, each GPIO is configured as an input with
a pullup to DVDDIO. In addition, each GPIO can be
programmed to cause an interrupt (on falling or rising
edges). In stop mode, use any interrupt to wake-up the
device.
The port direction (PD) register determines the
input/output direction of each I/O. The port output (PO)
register contains the current state of the logic output
buffers. When an I/O is configured as an output, writing
to the PO register controls the output logic state.
Reading the PO register shows the current state of the
output buffers, independent of the data direction. The
SLAVE
MASTER
MASTER
SLAVE
0
MASTER
SLAVE
DVDDIO
DVDDIO
MISO
MOSI
SS
SCLK
25