MAXQ7670ATL+ Maxim Integrated Products, MAXQ7670ATL+ Datasheet - Page 4

• Manufacturer Part Number: MAXQ7670ATL+
• Description: Microcontrollers (MCU) MICROCNTRLR W/10-BIT ADC PGA 64KB FLASH & CAN INTRFCE
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ7670ATL+

• Processor Series: MAXQ
• Core: RISC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• Interface Type: SPI, JTAG, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Timers: 1
• Operating Supply Voltage: 4.5 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-EP-40
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Microcontroller with 12-Bit ADC,
PGA, 64KB Flash, and CAN Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
noted. Typical values are at T
4
Channel Select Plus
Conversion Time
Turn-On Time
Aperture Delay
Aperture Jitter
Differential Input Voltage
Range
Absolute Input Voltage Range
Input Leakage Current
Input-Referred Noise
Small-Signal Bandwidth (-3dB)
Large-Signal Bandwidth (-3dB)
Input Capacitance (Note 8)
Input Common-Mode Rejection
Ratio
Power-Supply Rejection Ratio
EXTERNAL REFERENCE INPUTS
REFADC Input Voltage Range
REFADC Leakage Current
Input Capacitance
+3.3V (AVDD) LINEAR REGULATOR
AVDD Output Voltage
No-Load Quiescent Current
DVDDIO
_______________________________________________________________________________________
PARAMETER
= +5.0V, V
AVDD
= +3.3V, V
A
= +25°C.) (Note 1)
SYMBOL
t
t
CMRR
t
RECOV
PSRR
ACQ
CONV
DVDD
+
= +2.5V, V
PGA gain = 16V/V,
26.5 ADCCLK cycles at 2MHz
PGA gain = 1V/V,
16 ADCCLK cycles at 2MHz
At AIN0–AIN7, unipolar mode,
PGA gain = 1V/V
At AIN0–AIN7, unipolar mode,
PGA gain = 16V/V
At AIN0–AIN7, bipolar mode,
PGA gain = 1V/V
At AIN0–AIN7, bipolar mode,
PGA gain = 16V/V
At AIN0–AIN7
At AIN0–AIN7
At AIN0–AIN7, PGA gain = 16V/V
At AIN0–AIN7, PGA gain = 1V/V
V
V
V
V
Single-ended, any AIN0–AIN7,
PGA gain = 16V/V
Single-ended, any AIN0–AIN7,
PGA gain = 1V/V
AIN0–AIN7,
V
AV
ADC disabled
(Note 9)
LRAPD = 0
LRAPD = 0, all internal analog
peripherals disabled
IN
IN
IN
IN
CM
DD
= 12mV
= 200mV
= 150mV
= 2.5V
= differential input range
= 3.0V to 3.6V
REFADC
P-P
CONDITIONS
P-P
P-P
P-P
, PGA gain = 1V/V
, PGA gain = 16V/V
= +3.3V, system clock = 16MHz. T
, PGA gain = 1V/V
, PGA gain =16V/V
-V
-V
REFADC
REFADC
3.15
MIN
/32
1.0
/2
0
0
0
A
= T
13.25
±0.1
TYP
100
400
3.3
3.3
10
60
50
33
23
33
19
16
13
75
90
20
10
MIN
8
1
to T
+V
+V
MAX
V
V
V
REFADC
0.125
MAX
REFADC
REFADC
3.45
AVDD
AVDD
/32
, unless otherwise
/2
UNITS
µV
ps
MHz
MHz
µA
dB
dB
µA
µA
µs
µs
ns
pF
pF
RMS
V
V
V
V
P-P