WM9712LGEFL/V Wolfson Microelectronics, WM9712LGEFL/V Datasheet - Page 55
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WM9712LGEFL/V
Manufacturer Part Number
WM9712LGEFL/V
Description
Multimedia Misc Stereo AC'97 CODEC T/P Interface
Manufacturer
Wolfson Microelectronics
Type
Audio and Touchpanel Codecr
Datasheet
1.WM9712LGEFLV.pdf
(77 pages)
Specifications of WM9712LGEFL/V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 25 C
Mounting Style
SMD/SMT
Package / Case
QFN
Audio Codec Type
Stereo
No. Of Adcs
3
No. Of Dacs
3
No. Of Input Channels
8
No. Of Output Channels
4
Adc / Dac Resolution
12bit
Adcs / Dacs Signal To Noise Ratio
94dB
Sampling Rate
48kHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
WM9712LGEFL/V
Manufacturer:
VISHAY
Quantity:
1 000
Production Data
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POWER MANAGEMENT
The WM9712L includes the standard power down control register defined by the AC’97 specification
(register 26h). Additionally, it also allows more specific control over the individual blocks of the device
through register 24h. Each particular circuit block is active when both the relevant bit in register 26h
AND the relevant bit in register 24h are set to ‘0’.
Table 41 Powerdown and Status Register (Conforms to AC’97 Rev 2.2)
As can be seen from the table above, most blocks are ‘ON’ by default. However, if pin 47
(GPIO4/ADA/MASK) is held high during reset, the WM9712L starts up with all blocks powered down
by default, saving power. This is achieved by connecting a pull-up resistor (e.g. 100kΩ) from pin 47
to DBVDD. Note that the state of pin 47 during reset only affects register 26h.
26h
Powerdown/
Status
register
REGISTER
ADDRESS
BIT
14
13
12
11
10
9
8
3
2
1
0
LABEL
DAC
ADC
PR6
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
NORMAL
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
1
1
1
1
DEFAULT
PIN 47 ‘HI’
DURING
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
RESET
0
0
0
0
Disables HPOUTL, HPOUTR and
OUT3 Buffer
Disables internal clock
Disables AC-link interface
(external clock off)
Disables VREF, analogue mixers
and outputs
Disables analogue mixers,
LOUT2, ROUT2 (but not VREF)
Disables stereo DAC
Disables audio ADCs and input
Mux
Read-only bit, indicates VREF is
ready (inverse of PR2)
Read-only bit, indicates analogue
mixers are ready (inverse of PR3)
Read-only bit, indicates audio
DACs are ready (inverse of PR1)
Read-only bit, indicates audio
ADCs are ready (inverse of PR0)
DESCRIPTION
PD Rev 4.5 August 2006
WM9712L
55