ispPAC-POWR1220AT8-01TN100I Lattice, ispPAC-POWR1220AT8-01TN100I Datasheet - Page 22

• Manufacturer Part Number: ispPAC-POWR1220AT8-01TN100I
• Description: Supervisory Circuits Prec. Power Supply Seq. Monitor Marg.
• Manufacturer: Lattice
• Type: E2CMOSr
• Series: ispPAC®r

Specifications of ispPAC-POWR1220AT8-01TN100I

• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Number Of Voltages Monitored: 12
• Monitored Voltage: Adj
• Undervoltage Threshold: Adj
• Overvoltage Threshold: Adj
• Manual Reset: No
• Watchdog: No
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 40000 uA
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 85 C
• Package / Case: TQFP-100
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 1-11. ispPAC-POWR1220AT8 Macrocell Block Diagram
Clock and Timer Functions
Figure 1-12 shows a block diagram of the ispPAC-POWR1220AT8’s internal clock and timer systems. The master
clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived.
Figure 1-12. Clock and Timer System
The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer
clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir-
PT4
PT3
PT2
PT1
PT0
Clock
Polarity
Block Init Product Term
Oscillator
Internal
8MHz
SW0
Global Polarity Fuse for
Init Product Term
SW1
MCLK
Product Term Allocation
Global Reset
32
SW2
1-22
PLDCLK
Power On Reset
Timer 0
Timer 1
Timer 2
Timer 3
ispPAC-POWR1220AT8 Data Sheet
Macrocell flip-flop provides
D, T, or combinatorial
output with polarity
D/T
PLD Clock
R
CLK
To/From
P
Q
PLD
To ORP