ispPAC-POWR1220AT8-01TN100I Lattice, ispPAC-POWR1220AT8-01TN100I Datasheet - Page 50

• Manufacturer Part Number: ispPAC-POWR1220AT8-01TN100I
• Description: Supervisory Circuits Prec. Power Supply Seq. Monitor Marg.
• Manufacturer: Lattice
• Type: E2CMOSr
• Series: ispPAC®r

Specifications of ispPAC-POWR1220AT8-01TN100I

• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Number Of Voltages Monitored: 12
• Monitored Voltage: Adj
• Undervoltage Threshold: Adj
• Overvoltage Threshold: Adj
• Manual Reset: No
• Watchdog: No
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 40000 uA
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 85 C
• Package / Case: TQFP-100
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 40mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispPAC-POWR1220AT8 Data Sheet
2
UES_PROGRAM – This instruction will program the content of the UES Register into the UES E
CMOS memory.
The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces
the outputs into the OUTPUTS_HIGHZ.
ERASE_DONE_BIT – This instruction clears the 'Done' bit, which prevents the ispPAC-POWR1220AT8 sequence
from starting.
PROGRAM_DONE_BIT – This instruction sets the 'Done' bit, which enables the ispPAC-POWR1220AT8
sequence to start.
RESET – This instruction resets the PLD sequence and output macrocells.
IN1_RESET_JTAG_BIT – This instruction clears the JTAG Register logic input 'IN1.' The PLD input has to be con-
figured to take input from the JTAG Register in order for this command to have effect on the sequence.
IN1_SET_JTAG_BIT – This instruction sets the JTAG Register logic input 'IN1.' The PLD input has to be config-
ured to take input from the JTAG Register in order for this command to have effect on the sequence.
PLD_VERIFY_INCR – This instruction reads out the PLD data register for the current address and increments the
address register for the next read.
Notes:
In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output
pins, in which the open-drains are tri-stated and the FET drivers are pulled low.
2
Before any of the above programming instructions are executed, the respective E
CMOS bits need to be erased
using the corresponding erase instruction.
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