LC4064V-5TN48C Lattice, LC4064V-5TN48C Datasheet - Page 25
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LC4064V-5TN48C
Manufacturer Part Number
LC4064V-5TN48C
Description
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Manufacturer
Lattice
Datasheet
1.LC4256V-75TN100I.pdf
(94 pages)
Specifications of LC4064V-5TN48C
Memory Type
EEPROM
Number Of Macrocells
64
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
400 MHz
Delay Time
2.5 ns
Number Of Programmable I/os
352
Operating Supply Voltage
3.3 V
Supply Current
12 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-48
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Package
48TQFP
Family Name
ispMACH® 4000V
Number Of Macro Cells
64
Maximum Propagation Delay Time
5 ns
Number Of User I/os
32
Number Of Logic Blocks/elements
36
Typical Operating Supply Voltage
3.3 V
Operating Temperature
0 to 90 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4064V-5TN48C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LC4064V-5TN48C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
ispMACH 4000Z External Switching Characteristics (Cont.)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
PD
PD_MC
S
ST
SIR
SIRZ
H
HT
HIR
HIRZ
CO
R
RW
PTOE/DIS
GPTOE/DIS
GOE/DIS
CW
GW
WIR
MAX
MAX
Parameter
4
(Ext.)
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay
through macrocell
GLB register setup time before clock
GLB register setup time before clock with T-
type register
GLB register setup time before clock, input
register path
GLB register setup time before clock with zero
hold
GLB register hold time after clock
GLB register hold time after clock with T-type
register
GLB register hold time after clock, input regis-
ter path
GLB register hold time after clock, input regis-
ter path with zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output
enable/disable
Input to output global product term output
enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transparent) or
high (for high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
clock frequency with external feedback, [1 /
(t
S
+ t
CO
)]
Description
Over Recommended Operating Conditions
1, 2, 3
25
Min.
200
150
2.9
3.1
1.3
2.6
0.0
0.0
1.3
0.0
2.0
1.8
1.8
1.8
—
—
—
—
—
—
—
ispMACH 4000V/B/C/Z Family Data Sheet
-45
Max.
10.0
4.5
5.8
3.8
7.5
8.2
5.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
139
200
3.0
3.2
1.3
2.6
0.0
0.0
1.3
0.0
2.0
2.0
2.0
2.0
—
—
—
—
—
—
—
-5
Max.
10.0
5.0
6.0
4.2
7.5
8.5
6.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
168
111
4.5
4.7
1.4
2.7
0.0
0.0
1.3
0.0
4.0
3.3
3.3
3.3
—
—
—
—
—
—
—
-75
Max.
10.5
7.5
8.0
4.5
9.0
9.0
7.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Timing v.2.2
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns