LC4064V-5TN48C Lattice, LC4064V-5TN48C Datasheet - Page 38
![CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD](/photos/16/2/160257/tqfp-48_sml.jpg)
LC4064V-5TN48C
Manufacturer Part Number
LC4064V-5TN48C
Description
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Manufacturer
Lattice
Datasheet
1.LC4256V-75TN100I.pdf
(94 pages)
Specifications of LC4064V-5TN48C
Memory Type
EEPROM
Number Of Macrocells
64
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
400 MHz
Delay Time
2.5 ns
Number Of Programmable I/os
352
Operating Supply Voltage
3.3 V
Supply Current
12 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-48
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Package
48TQFP
Family Name
ispMACH® 4000V
Number Of Macro Cells
64
Maximum Propagation Delay Time
5 ns
Number Of User I/os
32
Number Of Logic Blocks/elements
36
Typical Operating Supply Voltage
3.3 V
Operating Temperature
0 to 90 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4064V-5TN48C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LC4064V-5TN48C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
ispMACH 4000Z Timing Adders (Cont.)
Lattice Semiconductor
Optional Delay Adders
t
t
t
t
t
LVTTL_in
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
t
LVTTL_out
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
PCI_out
Slow Slew
Note: Open drain timing is the same as corresponding LVCMOS timing.
1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these
INDIO
EXP
ORP
BLA
IOI
IOO
adders.
Input Adjusters
Output Adjusters
Adder
Type
t
t
—
t
t
t
t
t
t
t
t
t
INREG
MCELL
ROUTE
IN,
IN,
IN,
IN,
IN,
BUF,
BUF,
BUF,
BUF,
BUF,
BUF,
t
t
t
t
t
Parameter
GCLK_IN,
GCLK_IN,
GCLK_IN,
GCLK_IN,
GCLK_IN,
t
t
t
t
t
t
EN,
EN,
EN,
EN,
EN,
EN
Base
t
t
t
t
t
DIS
DIS
DIS
DIS
DIS
t
t
t
t
t
GOE
GOE
GOE
GOE
GOE
Input register delay
Product term expander
delay
Output routing pool
delay
Additional block load-
ing adder
Using LVTTL standard
Using LVCMOS 3.3
standard
Using LVCMOS 2.5
standard
Using LVCMOS 1.8
standard
Using PCI compatible
input
Output configured as
TTL buffer
Output configured as
3.3V buffer
Output configured as
2.5V buffer
Output configured as
1.8V buffer
Output configured as
PCI compatible buffer
Output configured for
slow slew rate
Description
38
1
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ispMACH 4000V/B/C/Z Family Data Sheet
-45
Max.
1.30
0.45
0.40
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
1.30
0.45
0.40
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-75
Max.
1.30
0.50
0.40
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Timing v.2.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns